kern/143427: [agp] Patch for D510 pinetail AGP problem
Mark Linimon
linimon at lonesome.com
Tue Feb 2 00:10:04 UTC 2010
The following reply was made to PR kern/143427; it has been noted by GNATS.
From: Mark Linimon <linimon at lonesome.com>
To: bug-followup at FreeBSD.org
Cc:
Subject: Re: kern/143427: [agp] Patch for D510 pinetail AGP problem
Date: Mon, 1 Feb 2010 18:09:19 -0600
----- Forwarded message from Mamoru Sumida <msumida at mvc.biglobe.ne.jp> -----
From: Mamoru Sumida <msumida at mvc.biglobe.ne.jp>
To: linimon at FreeBSD.org
Cc: msumida at mvc.biglobe.ne.jp, freebsd-bugs at FreeBSD.org
Subject: Re: kern/143427: [agp] Patch for D510 pinetail AGP problem
Oops!! Have I forgot to attach the patch?
Here is
For
src/dev/apg/apg_i810.c
src/dev/drm/drm_pciids.h
src/dev/drm/i930_drv.h
src/dev/drm/i930_reg.h
Thanks
--- i915_drv.h.orig 2010-02-01 11:42:16.000000000 +0000
+++ i915_drv.h 2010-01-30 15:55:43.000000000 +0000
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/dev/drm/i915_drv.h,v 1.4.2.9 2009/10/30 16:38:53 rnoland Exp $");
+__FBSDID("$FreeBSD: src/sys/dev/drm/i915_drv.h,v 1.13.2.2 2009/10/30 16:37:58 rnoland Exp $");
#ifndef _I915_DRV_H_
#define _I915_DRV_H_
@@ -657,16 +657,23 @@
(dev)->pci_device == 0x2E32 || \
IS_GM45(dev))
+#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
+#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
+#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
+
#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
(dev)->pci_device == 0x29B2 || \
- (dev)->pci_device == 0x29D2)
+ (dev)->pci_device == 0x29D2 || \
+ (IS_IGD(dev)))
+
#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
- IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
-
+ IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
+ IS_IGD(dev))
+
#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
#define PRIMARY_RINGBUFFER_SIZE (128*1024)
--- i915_reg.h.orig 2010-02-01 11:41:26.000000000 +0000
+++ i915_reg.h 2010-01-30 15:59:15.000000000 +0000
@@ -23,7 +23,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/dev/drm/i915_reg.h,v 1.3.2.1.2.1 2009/10/25 01:10:29 kensmith Exp $");
+__FBSDID("$FreeBSD: src/sys/dev/drm/i915_reg.h,v 1.3.2.1 2009/08/03 08:13:06 kensmith Exp $");
#ifndef _I915_REG_H_
#define _I915_REG_H_
@@ -362,6 +362,7 @@
#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
+#define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
#define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
#define I915_CRC_ERROR_ENABLE (1UL<<29)
@@ -438,6 +439,7 @@
*/
#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
+#define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
/* i830, required in DVO non-gang */
#define PLL_P2_DIVIDE_BY_4 (1 << 23)
#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
@@ -504,10 +506,12 @@
#define FPB0 0x06048
#define FPB1 0x0604c
#define FP_N_DIV_MASK 0x003f0000
+#define FP_N_IGD_DIV_MASK 0x00ff0000
#define FP_N_DIV_SHIFT 16
#define FP_M1_DIV_MASK 0x00003f00
#define FP_M1_DIV_SHIFT 8
#define FP_M2_DIV_MASK 0x0000003f
+#define FP_M2_IGD_DIV_MASK 0x000000ff
#define FP_M2_DIV_SHIFT 0
#define DPLL_TEST 0x606c
#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
--- drm_pciids.h.orig 2010-02-01 11:37:35.000000000 +0000
+++ drm_pciids.h 2010-01-30 16:00:40.000000000 +0000
@@ -553,6 +553,8 @@
{0x8086, 0x2E12, CHIP_I9XX|CHIP_I965, "Intel Q45/Q43"}, \
{0x8086, 0x2E22, CHIP_I9XX|CHIP_I965, "Intel G45/G43"}, \
{0x8086, 0x2E32, CHIP_I9XX|CHIP_I965, "Intel G41"}, \
+ {0x8086, 0xA001, CHIP_I9XX|CHIP_I965, "Intel IGD"}, \
+ {0x8086, 0xA011, CHIP_I9XX|CHIP_I965, "Intel IGD"}, \
{0, 0, 0, NULL}
#define imagine_PCI_IDS \
--- agp_i810.c.orig 2010-02-01 11:36:11.000000000 +0000
+++ agp_i810.c 2010-01-30 16:28:27.000000000 +0000
@@ -70,6 +70,7 @@
CHIP_I915, /* 915G/915GM */
CHIP_I965, /* G965 */
CHIP_G33, /* G33/Q33/Q35 */
+ CHIP_IGD, /* G33 like IGD */
CHIP_G4X, /* G45/Q45 */
};
@@ -165,6 +166,10 @@
"Intel Q33 SVGA controller"},
{0x2A028086, CHIP_I965, 0x00020000,
"Intel GM965 SVGA controller"},
+ {0xA0018086, CHIP_IGD, 0x00010000,
+ "Intel IGD SVGA controller"},
+ {0xA0118086, CHIP_IGD, 0x00010000,
+ "Intel IGD SVGA controller"},
{0x2A128086, CHIP_I965, 0x00020000,
"Intel GME965 SVGA controller"},
{0x2A428086, CHIP_G4X, 0x00020000,
@@ -286,6 +291,7 @@
case CHIP_I915:
case CHIP_I965:
case CHIP_G33:
+ case CHIP_IGD:
case CHIP_G4X:
deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
if ((deven & AGP_I915_DEVEN_D2F0) ==
@@ -351,6 +357,7 @@
case CHIP_I915:
case CHIP_I965:
case CHIP_G33:
+ case CHIP_IGD:
case CHIP_G4X:
device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
@@ -386,6 +393,7 @@
break;
case CHIP_I915:
case CHIP_G33:
+ case CHIP_IGD:
sc->sc_res_spec = agp_i915_res_spec;
agp_set_aperture_resource(dev, AGP_I915_GMADR);
break;
@@ -401,7 +409,8 @@
return error;
if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
- sc->chiptype != CHIP_G4X && ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
+ sc->chiptype != CHIP_IGD && sc->chiptype != CHIP_G4X &&
+ ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
{
device_printf(dev, "agp_i810.c does not support physical "
"memory above 4GB.\n");
@@ -491,7 +500,7 @@
gatt->ag_physical = pgtblctl & ~1;
} else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
- sc->chiptype == CHIP_G4X) {
+ sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
unsigned int gcc1, pgtblctl, stolen, gtt_size;
/* Stolen memory is set up at the beginning of the aperture by
@@ -553,6 +562,7 @@
return EINVAL;
}
break;
+ case CHIP_IGD:
case CHIP_G4X:
gtt_size = 0;
break;
@@ -587,6 +597,7 @@
if (sc->chiptype == CHIP_I915 ||
sc->chiptype == CHIP_I965 ||
sc->chiptype == CHIP_G33 ||
+ sc->chiptype == CHIP_IGD ||
sc->chiptype == CHIP_G4X) {
stolen = 48 * 1024;
} else {
@@ -597,6 +608,7 @@
if (sc->chiptype == CHIP_I915 ||
sc->chiptype == CHIP_I965 ||
sc->chiptype == CHIP_G33 ||
+ sc->chiptype == CHIP_IGD ||
sc->chiptype == CHIP_G4X) {
stolen = 64 * 1024;
} else {
@@ -606,6 +618,7 @@
case AGP_G33_GCC1_GMS_STOLEN_128M:
if (sc->chiptype == CHIP_I965 ||
sc->chiptype == CHIP_G33 ||
+ sc->chiptype == CHIP_IGD ||
sc->chiptype == CHIP_G4X) {
stolen = 128 * 1024;
} else {
@@ -615,6 +628,7 @@
case AGP_G33_GCC1_GMS_STOLEN_256M:
if (sc->chiptype == CHIP_I965 ||
sc->chiptype == CHIP_G33 ||
+ sc->chiptype == CHIP_IGD ||
sc->chiptype == CHIP_G4X) {
stolen = 256 * 1024;
} else {
@@ -783,6 +797,7 @@
case CHIP_I915:
case CHIP_I965:
case CHIP_G33:
+ case CHIP_IGD:
case CHIP_G4X:
return agp_generic_set_aperture(dev, aperture);
}
@@ -803,7 +818,7 @@
pte = (u_int32_t)physical | 1;
if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
- sc->chiptype == CHIP_G4X) {
+ sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
pte |= (physical & 0x0000000f00000000ull) >> 28;
} else {
/* If we do actually have memory above 4GB on an older system,
@@ -822,6 +837,7 @@
AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
break;
case CHIP_I915:
+ case CHIP_IGD:
case CHIP_G33:
bus_write_4(sc->sc_res[1],
(offset >> AGP_PAGE_SHIFT) * 4, pte);
----- End forwarded message -----
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