[Differential] [Updated, 25 lines] D3093: ARM64 TCR register update

[wma_semihalf.com (Wojciech Macek)]

wma_semihalf.com updated this revision to Diff 7005.

REPOSITORY
  rS FreeBSD src repository

CHANGES SINCE LAST UPDATE
  https://reviews.freebsd.org/D3093?vs=7000&id=7005

REVISION DETAIL
  https://reviews.freebsd.org/D3093

AFFECTED FILES
  sys/arm64/arm64/locore.S
  sys/arm64/include/armreg.h

CHANGE DETAILS
  diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
  --- a/sys/arm64/include/armreg.h
  +++ b/sys/arm64/include/armreg.h
  @@ -200,6 +200,28 @@
   #define	TCR_TG1_4K	(2 << TCR_TG1_SHIFT)
   #define	TCR_TG1_64K	(3 << TCR_TG1_SHIFT)
   
  +#define	TCR_SH1_SHIFT	28
  +#define	TCR_SH1_IS	(0x3UL << TCR_SH1_SHIFT)
  +#define	TCR_ORGN1_SHIFT	26
  +#define	TCR_ORGN1_WBWA	(0x1UL << TCR_ORGN1_SHIFT)
  +#define	TCR_IRGN1_SHIFT	24
  +#define	TCR_IRGN1_WBWA	(0x1UL << TCR_IRGN1_SHIFT)
  +#define	TCR_SH0_SHIFT	12
  +#define	TCR_SH0_IS	(0x3UL << TCR_SH0_SHIFT)
  +#define	TCR_ORGN0_SHIFT	10
  +#define	TCR_ORGN0_WBWA	(0x1UL << TCR_ORGN0_SHIFT)
  +#define	TCR_IRGN0_SHIFT	8
  +#define	TCR_IRGN0_WBWA	(0x1UL << TCR_IRGN0_SHIFT)
  +
  +#define	TCR_CACHE_ATTRS	((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
  +				(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
  +
  +#ifdef SMP
  +#define	TCR_SMP_ATTRS	(TCR_SH0_IS | TCR_SH1_IS)
  +#else
  +#define	TCR_SMP_ATTRS	0
  +#endif
  +
   #define	TCR_T1SZ_SHIFT	16
   #define	TCR_T0SZ_SHIFT	0
   #define	TCR_TxSZ(x)	(((x) << TCR_T1SZ_SHIFT) | ((x) << TCR_T0SZ_SHIFT))
  diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
  --- a/sys/arm64/arm64/locore.S
  +++ b/sys/arm64/arm64/locore.S
  @@ -535,7 +535,8 @@
   		/* Device            Normal, no cache     Normal, write-back */
   	.quad	MAIR_ATTR(0x00, 0) | MAIR_ATTR(0x44, 1) | MAIR_ATTR(0xff, 2)
   tcr:
  -	.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K)
  +	.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K | \
  +	    TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
   sctlr_set:
   	/* Bits to set */
   	.quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \

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To: wma_semihalf.com, zbb, emaste, andrew
Cc: imp, andrew, freebsd-arm-list, emaste
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