[Differential] [Request, 54 lines] D1812: Resolve cache line size from CP15

zbb (Zbigniew Bodek) phabric-noreply at FreeBSD.org
Mon Feb 9 11:59:52 UTC 2015


zbb created this revision.
zbb added reviewers: ian, andrew.
zbb added a subscriber: freebsd-arm.

REVISION SUMMARY
  Switch the cache line size during invalidations/flushes to be read from CP15 cache type register.
  
  Submitted by:    Wojciech Macek <wma at semihalf.com>
  Obtained from:   Semihalf

REVISION DETAIL
  https://reviews.freebsd.org/D1812

AFFECTED FILES
  sys/arm/arm/cpufunc.c
  sys/arm/arm/cpufunc_asm_armv7.S
  sys/arm/arm/elf_trampoline.c
  sys/arm/include/armreg.h

To: zbb, ian, andrew
Cc: freebsd-arm


More information about the freebsd-arm mailing list