gic.c and interrupt priority mask register (GICC_PMR)

[Thomas Skibo]

Hello.

I mentioned this as an aside in another email but I'd like to revisit it.

My Zynq port doesn't work unless I initialize the GIC interrupt priority 
mask register (GICC_PMR) which I do in a hack in zy7_machdep.c.  The 
GICC_PMR register is never touched in gic.c and I wonder how other ARM 
ports work without having it initialized.  I figure either they use a 
different interrupt controller, their GIC implementation has a different 
reset value for the PMR, or a boot-loader sets up the register before 
the kernel is entered.

The ARM Generic Interrupt Controller Architecture Specification (version 
2.0) states that the reset value of GICC_PMR is 0 which masks all 
interrupts.  So shouldn't gic.c initialize it to 0xff if the PMR 
functionality isn't used?

--Thomas

Something like this?

Index: sys/arm/arm/gic.c
===================================================================
--- sys/arm/arm/gic.c	(revision 249650)
+++ sys/arm/arm/gic.c	(working copy)
@@ -134,6 +134,9 @@
  	/* Enable CPU interface */
  	gic_c_write_4(GICC_CTLR, 1);

+	/* Set priority mask register. */
+	gic_c_write_4(GICC_PMR, 0xff);
+
  	/* Enable interrupt distribution */
  	gic_d_write_4(GICD_CTLR, 0x01);
  		
@@ -199,6 +202,9 @@
  	/* Enable CPU interface */
  	gic_c_write_4(GICC_CTLR, 1);

+	/* Set priority mask register. */
+	gic_c_write_4(GICC_PMR, 0xff);
+
  	/* Enable interrupt distribution */
  	gic_d_write_4(GICD_CTLR, 0x01);




-- 
--------
Thomas Skibo
ThomasSkibo at sbcglobal.net