FreeBSD/armv6z/clang on Raspberry Pi 512MB (with U-Boot + ubldr)
gonzo at bluezbox.com
Thu Dec 27 04:16:22 UTC 2012
On 2012-12-26, at 7:52 PM, Daisuke Aoyama <aoyama at peach.ne.jp> wrote:
>> PTE sync - related part, Im not sure it's strictly required. We use WT caches for page tables
>> so we should be OK without implicit sync operations for them. I hope somebody
>> more clueful can confirm/disprove this.
> Some digging, I notice "Invalidate Entire Instruction Cache" works without segfault.
> So, Invalidate D-cache is no effect :)
> It seems following should work for this issue:
> mov r0, #0
> mcr p15, 0, r0, c7, c5, 0 /* Invalidate Entire Instruction Cache */
> mcr p15, 0, r0, c7, c10, 4 /* Data Synchronization Barrier */
> Try this code instead of CF_ICACHE_SYNC.
> I don't know side effect of Invalidate I-cache, but it works.
> Also I don't know whether DSB is required or not.
> For test, using NFS or HDD/SDD is BAD idea for system stress.
> You must use SD(mmc) or USB memory. Serial console is recommended for interrupt test.
> Here is simple test from serial console:
> # rm -rf /var/db/portsnap /usr/ports
> # mkdir /var/db/portsnap
> # portsnap fetch
> # portsnap extract
> # cd /usr/ports/shells/bash
> # make BATCH=y
> If your kernel is really stable, it should finish without any problems with SD/mmc.
Hmm, I saw problems with i-caches with kernel with WB cache enabled instead of WT.
This patch fixed it for me:
It invalidates i-caches only when new mapping is created, not on every switch so
it should be less taxing on performance.
Could you test it on your setup?
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