Fwd: Re: EHCI on armv6 with Write-Back caches

[Ian Lepore]

On Thu, 2012-12-20 at 19:56 +0100, Hans Petter Selasky wrote:
> FYI - please test!
> 
> ----------  Forwarded Message  ----------
> 
> Subject: Re: EHCI on armv6 with Write-Back caches
> Date: Thursday 20 December 2012, 19:46:34
> From: Hans Petter Selasky <hselasky at c2i.net>
> To: Warner Losh <imp at bsdimp.com>
> CC: Andrew Turner <andrew at fubar.geek.nz>, Oleksandr Tymoshenko 
> <gonzo at freebsd.org>, freebsd-usb at freebsd.org, alfred at freebsd.org, freebsd-
> wireless at freebsd.org
> 
> Hi,
> 
> I've run some basic tests over here (x86) which passed after some patch 
> modifications. Please test and verify for your ARM targets:
> 
> http://svnweb.freebsd.org/changeset/base/244500
> http://svnweb.freebsd.org/changeset/base/244503
> 
> Please also verify that upgt and uwrt and uath still works like expected.
> 
> --HPS

FYI, I've done some testing (it was weeks ago) of EHCI on armv4 and had
no problems at all.  I didn't exactly beat it to death, but I know I
tested umass in particular with some file copying and tar/untar and that
sort of thing.  I'll make a point of updating and re-testing that soon.

If there have been problems on armv6, especially with the memory shared
between the cpu and hci (the descriptor lists), there's a chance it's
fallout from the change in busdma_machdep-armv6.c in August to stop
honoring BUS_DMAMEM_COHERENT (r239597).  While the docs don't require
that flag to be honored, the practical reality is that drivers are
relying on the fact that the ARM and MIPS implementations treat that
flag as if it were BUS_DMAMEM_NOCACHE.

As of r244469 (yesterday) the COHERENT flag will hand out uncached
memory again, so if the shared descriptor lists were any part of the
problem, that should be fixed now.

-- Ian