arm cache fixes

[Ian Lepore]

Yes, I've submitted yet another patch for an arm cache maintenance bug. 

Just to be clear: it is NOT the fix for the arm v6/v7 writeback problem.

It also doesn't apply to Marvell/Sheeva-based armv5 systems, because
they have their own SoC-specific cache maintenance routines.

It does apply to most other armv4 and v5 systems.

Speaking of the armv6/v7 bug that happens with writeback enabled... I
took a hard look at the low-level asm code for those, and nothing jumps
out at me as wrong.  But then, I've looked at the armv4 low level
routines many times before, starting in 2009 when I first started
fighting cache coherency problems, and I never noticed those incorrect
'bpl' instructions before.  (I've been doing arm asm since 1993, and I'm
still always tripped up by the branch mnemonics used with arm.)

I've been calling it "the armv6/v7" problem, but do we know whether it's
both of those architectures, or if it's v7-only?  There's a huge
difference between the cache maintenance schemes for the two.  If it
happens on both, we should probably focus on the busdma_machdep code.
If it's v7 only, maybe it's low-level code (which looks reasonable on
its face, but I need to study the ARM ARM for v7 stuff more).

-- Ian