FreeBSD on Raspberry Pi 512MB (with U-Boot + ubldr)

Warner Losh imp at
Mon Dec 3 17:16:15 UTC 2012

On Dec 3, 2012, at 9:33 AM, Ian Lepore wrote:

> On Mon, 2012-12-03 at 09:17 -0700, Warner Losh wrote:
>> On Dec 3, 2012, at 7:51 AM, Daisuke Aoyama wrote:
>>>>>> BTW, SDHCI is not yet stable?
>>>>> There is one issue with setting SDHCI clock. I'll commit fix later today.
>>>> I like to share some information about the SD card reading speed.
>>>> While exchanging the old boot sequence with then new one I once booted
>>>> with the new boot sequence but without an /boot/loader.rc file.
>>>> The reading speed achieved with
>>>> dd if=/dev/mmcsd0 of=/dev/null bs=1m count=100
>>>> from the SD card was 10 Mbyte/sec.
>>>> After creating the file with "echo 'fdt addr 0x100' > /boot/loader.rc"
>>>> and rebooting the reading speed achieved from the SD card was down to
>>>> 2.8 Mbyte/sec.
>>>> Although the SDHCI frequency was shown on the second boot as double high as
>>>> on the first (100MHz versus 50MHz) the reading speed was much lower.
>>>> I think the cause was the mmcsd bus bit width which was reported as 4 at
>>>> the first and as 1 at the second boot.
>>> At this time, it must be 50. if use 100MHz, some cards cant be used anymore.
>>> Howerver, probably 4bit transfer is OK.
>> 33MHz is the top speed for SD cards.  There's an extension to make them go as fast as 50MHz.  Most SD cards cope at 50MHz without enabling the extension and even more when enabled.  The current common code tries to enable things properly, but relies on the host bridge adapter driver to set the clock properly...  There may be some cruft here left over from the early Atmel legacy where the datasheet gave somewhat aggressive advise..
>> 100MHz at one bit is 100Mbps.  50MHz 4 bit is 200Mbps.
>> I gotta get a pi to play around with this :)
> Oops, not quite.
> SD 1.0 and 1.1 limit bus speed to 25mhz, but you can usually get away
> with 30mhz and sometimes even higher (but anything over 25 is out of
> spec).  
> SD 2.0 upped the limit to 50mhz, but you can't set the bus to run that
> fast until you've probed the card and determined that it supports SDHC.
> The signaling standard is actually different between 1.x and 2.x in SDHC
> mode (there are differences in the relationships between rise/fall/hold
> times above 25mhz).  That's why old Atmel hardware can't do SDHC 50mhz
> even though the microcontroller can run the bus at 50mhz -- it does so
> with the 1.x signal timings (it was pretty sneaky of them to adverise
> mmc/sd up to 50mhz knowing that running the bus that fast was just a
> violation of the SD 1.x spec, which is all they really support).
> I've heard that SD 3.x allows for bus speeds of 100mhz and higher, but
> only on SDXC cards.  I'm hand-waving a bit here because I haven't gotten
> to work with hardware that new yet.

Thanks for refreshing my memory...

> Bus speed is independant of the 1/4/8 bit datapath (well, at least in
> the SD specs up through 2.0, after that I'm not sure).

Experience has shown that the card has a speed limit for transfer though, so I've seen cards that can do 1 bit at 50MHz but not 4 bits at 25MHz.


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