arm/156814: OpenRD Ultimate does not boot on DB-88F6XXX or
SHEEVAPLUG kernel configurations
Arnaud
vancorte at biologie.ens.fr
Wed May 4 13:30:17 UTC 2011
>Number: 156814
>Category: arm
>Synopsis: OpenRD Ultimate does not boot on DB-88F6XXX or SHEEVAPLUG kernel configurations
>Confidential: no
>Severity: non-critical
>Priority: low
>Responsible: freebsd-arm
>State: open
>Quarter:
>Keywords:
>Date-Required:
>Class: sw-bug
>Submitter-Id: current-users
>Arrival-Date: Wed May 04 13:30:10 UTC 2011
>Closed-Date:
>Last-Modified:
>Originator: Arnaud
>Release: 9.0-CURRENT
>Organization:
Ecole Normale Superieure
>Environment:
FreeBSD OpenRD-Ultimate 9.0-CURRENT FreeBSD 9.0-CURRENT #0: Tue May 3 14:31:36 UTC 2011 root at OpenRD-Ultimate:/usr/obj/usr/src/sys/OPENRD-FBSD9 arm
>Description:
Hi,
I was not able to boot my OpenRD Ultimate using DB-88F6XXX or SHEEVAPLUG kernels which are designed for device configurations close to mine.
Here is the solution I found, notably based on N.Shigemura work.
Two problems have been solved:
- boot by modifying the FDT
- use the two mge network interfaces
>How-To-Repeat:
Load one of these kernels, it should freeze the openrd box
>Fix:
Referring to an almost 1 year old thread (http://markmail.org/message/4vjllpvhotkshg6n), I have been able to have a working configuration with those modifications :
- create an OPENRD kernel config based on DB-88F6XXX
- using the openrd.dts file (written by N.Shigemura)
- applying the patch of N.shigemura on mge driver
- patching mgevar headers
I send you a diff of my modifications.
I am aware that some of these modifications could be a step back in developments that have been made during last months. I hope it will help developers.
Regards.
Patch attached with submission follows:
diff -Nur src/sys/arm/conf/OPENRD src/sys/arm/conf/OPENRD
--- src/sys/arm/conf/OPENRD 1970-01-01 00:00:00.000000000 +0000
+++ src/sys/arm/conf/OPENRD 2011-05-04 13:57:37.000000000 +0000
@@ -0,0 +1,90 @@
+#
+# Custom kernel for Marvell OpenRD devices.
+#
+#
+#
+
+ident OPENRD
+include "../mv/kirkwood/std.db88f6xxx"
+
+options SOC_MV_KIRKWOOD
+makeoptions MODULES_OVERRIDE=""
+
+#makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+makeoptions WERROR="-Werror"
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options INET6 #IPv6 communications protocols
+options FFS #Berkeley Fast Filesystem
+options NFSCLIENT #Network Filesystem Client
+options NFSLOCKD #Network Lock Manager
+options NFS_ROOT #NFS usable as /, requires NFSCLIENT
+options BOOTP
+options BOOTP_NFSROOT
+options BOOTP_NFSV3
+options BOOTP_WIRED_TO=mge0
+
+#options ROOTDEVNAME=\"ufs:/dev/da0a\"
+
+options SYSVSHM #SYSV-style shared memory
+options SYSVMSG #SYSV-style message queues
+options SYSVSEM #SYSV-style semaphores
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+options MUTEX_NOINLINE
+options RWLOCK_NOINLINE
+options NO_FFS_SNAPSHOT
+options NO_SWAPPING
+
+# Debugging
+options ALT_BREAK_TO_DEBUGGER
+options DDB
+#options DEADLKRES #Enable the deadlock resolver
+options DIAGNOSTIC
+#options INVARIANTS #Enable calls of extra sanity checking
+#options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+options KDB
+options WITNESS #Enable checks to detect deadlocks and cycles
+options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+#options WITNESS_KDB
+
+device pci
+
+# Pseudo devices
+device loop
+device md
+device pty
+device random
+
+# Serial ports
+device uart
+
+# Networking
+device ether
+device mge # Marvell Gigabit Ethernet controller
+device mii
+device e1000phy
+device bpf
+
+# USB
+options USB_DEBUG # enable debug msgs
+device usb
+device ehci
+device umass
+device scbus
+device pass
+device da
+
+# I2C (TWSI)
+device iic
+device iicbus
+
+# SATA
+device mvs
+device ata
+device atadisk
+
+# Flattened Device Tree
+options FDT
+options FDT_DTB_STATIC
+makeoptions FDT_DTS_FILE=openrd.dts
diff -Nur src/sys/boot/fdt/dts/openrd.dts src/sys/boot/fdt/dts/openrd.dts
--- src/sys/boot/fdt/dts/openrd.dts 1970-01-01 00:00:00.000000000 +0000
+++ src/sys/boot/fdt/dts/openrd.dts 2011-05-04 13:52:17.000000000 +0000
@@ -0,0 +1,354 @@
+/*
+ * Copyright (c) 2009-2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * OpenRD-Client/Ultimate Device Tree Source.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,OpenRD-CL";
+ compatible = "OpenRD-CL";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ mpp = &MPP;
+ pci0 = &pci0;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ soc = &SOC;
+ sram = &SRAM;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR131";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>; // 512M at 0x0
+ };
+
+ localbus at f1000000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x0f 0xf9300000 0x00100000
+ 0x1 0x1e 0xfa000000 0x00100000
+ 0x2 0x1d 0xfa100000 0x02000000
+ 0x3 0x1b 0xfc100000 0x00000400>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ led at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "led";
+ reg = <0x1 0x0 0x00100000>;
+ };
+
+ nor at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x2 0x0 0x02000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand at 3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x3 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ SOC: soc88f6281 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <1>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x34>;
+ pin-count = <50>;
+ pin-map = <
+ 0 1 /* MPP[0]: NF_IO[2] */
+ 1 1 /* MPP[1]: NF_IO[3] */
+ 2 1 /* MPP[2]: NF_IO[4] */
+ 3 1 /* MPP[3]: NF_IO[5] */
+ 4 1 /* MPP[4]: NF_IO[6] */
+ 5 1 /* MPP[5]: NF_IO[7] */
+ 6 1 /* MPP[6]: SYSRST_OUTn */
+ 7 0 /* MPP[7]: GPO[7] */
+ 8 1 /* MPP[8]: TW_SDA */
+ 9 1 /* MPP[9]: TW_SCK */
+ 10 3 /* MPP[10]: UA0_TXD */
+ 11 3 /* MPP[11]: UA0_RXD */
+ 12 1 /* MPP[12]: SD_CLK */
+ 13 1 /* MPP[13]: SD_CMD */
+ 14 1 /* MPP[14]: SD_D[0] */
+ 15 1 /* MPP[15]: SD_D[1] */
+ 16 1 /* MPP[16]: SD_D[2] */
+ 17 1 /* MPP[17]: SD_D[3] */
+ 18 1 /* MPP[18]: NF_IO[0] */
+ 19 1 /* MPP[19]: NF_IO[1] */
+ 20 3 /* MPP[20]: GE1[0] */
+ 21 3 /* MPP[21]: GE1[1] */
+ 22 3 /* MPP[22]: GE1[2] */
+ 23 3 /* MPP[23]: GE1[3] */
+ 24 3 /* MPP[24]: GE1[4] */
+ 25 3 /* MPP[25]: GE1[5] */
+ 26 3 /* MPP[26]: GE1[6] */
+ 27 3 /* MPP[27]: GE1[7] */
+ 28 0 /* MPP[28]: GPIO[28] */
+ 29 1 /* MPP[29]: TSMP[9] */
+ 30 3 /* MPP[30]: GE1[10] */
+ 31 3 /* MPP[31]: GE1[11] */
+ 32 3 /* MPP[32]: GE1[12] */
+ 33 3 /* MPP[33]: GE1[13] */
+ 34 0 /* MPP[34]: GPIO[34] */
+ 35 2 /* MPP[35]: TDM_CH0_TX_QL */
+ 36 2 /* MPP[36]: TDM_SPI_CS1 */
+ 37 2 /* MPP[37]: TDM_CH2_TX_QL */
+ 38 2 /* MPP[38]: TDM_CH2_RX_QL */
+ 39 4 /* MPP[39]: AU_I2SBCLK */
+ 40 4 /* MPP[40]: AU_I2SDO */
+ 41 4 /* MPP[41]: AU_I2SLRCLK */
+ 42 4 /* MPP[42]: AU_I2SMCLK */
+ 43 4 /* MPP[43]: AU_I2SDI */
+ 44 4 /* MPP[44]: AU_EXTCLK */
+ 45 2 /* MPP[45]: TDM_PCLK */
+ 46 2 /* MPP[46]: TDM_FS */
+ 47 2 /* MPP[47]: TDM_DRX */
+ 48 2 /* MPP[48]: TDM_DTX */
+ 49 2>; /* MPP[49]: TDM_CH0_TX_QL */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <35 36 37 38 39 40 41>;
+ interrupt-parent = <&PIC>;
+ };
+
+ rtc at 10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <12 13 14 11 46>;
+ interrupt-parent = <&PIC>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+ };
+ };
+
+ enet1: ethernet at 76000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x76000 0x2000>;
+ ranges = <0x0 0x76000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <16 17 18 15 47>;
+ interrupt-parent = <&PIC>;
+
+ mdio at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+ };
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <33>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <34>;
+ interrupt-parent = <&PIC>;
+ };
+
+ crypto at 30000 {
+ compatible = "mrvl,cesa";
+ reg = <0x30000 0x10000>;
+ interrupts = <22>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <48 19>;
+ interrupt-parent = <&PIC>;
+ };
+
+ xor at 60000 {
+ compatible = "mrvl,xor";
+ reg = <0x60000 0x1000>;
+ interrupts = <5 6 7 8>;
+ interrupt-parent = <&PIC>;
+ };
+
+ sata at 80000 {
+ compatible = "mrvl,sata";
+ reg = <0x80000 0x6000>;
+ interrupts = <21>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ SRAM: sram at fd000000 {
+ compatible = "mrvl,cesa-sram";
+ reg = <0xfd000000 0x00100000>;
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+
+ pci0: pcie at f1040000 {
+ compatible = "mrvl,pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf1040000 0x2000>;
+ bus-range = <0 255>;
+ ranges = <0x02000000 0x0 0xf4000000 0xf4000000 0x0 0x04000000
+ 0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&PIC>;
+ interrupts = <44>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x1 */
+ 0x0800 0x0 0x0 0x1 &PIC 0x9
+ 0x0800 0x0 0x0 0x2 &PIC 0x9
+ 0x0800 0x0 0x0 0x3 &PIC 0x9
+ 0x0800 0x0 0x0 0x4 &PIC 0x9
+ >;
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0xf4000000
+ 0x02000000 0x0 0xf4000000
+ 0x0 0x04040000
+
+ 0x01000000 0x0 0x0
+ 0x01000000 0x0 0x0
+ 0x0 0x00100000>;
+ };
+ };
+};
+
diff -Nur src/sys/dev/mge/if_mge.c src/sys/dev/mge/if_mge.c
--- src/sys/dev/mge/if_mge.c 2011-05-04 13:45:36.000000000 +0000
+++ src/sys/dev/mge/if_mge.c 2011-05-04 13:52:59.000000000 +0000
@@ -626,10 +626,9 @@
mge_attach(device_t dev)
{
struct mge_softc *sc;
- struct mii_softc *miisc;
struct ifnet *ifp;
uint8_t hwaddr[ETHER_ADDR_LEN];
- int i, error, phy;
+ int i, error;
sc = device_get_softc(dev);
sc->dev = dev;
@@ -642,8 +641,8 @@
mge_ver_params(sc);
/* Get phy address from fdt */
- if (fdt_get_phyaddr(sc->node, &phy) != 0)
- return (ENXIO);
+ if (fdt_get_phyaddr(sc->node, &sc->phyaddr) != 0)
+ sc->phyaddr = -1;
/* Initialize mutexes */
mtx_init(&sc->transmit_lock, device_get_nameunit(dev), "mge TX lock", MTX_DEF);
@@ -674,6 +673,9 @@
sc->tx_ic_time = 768;
mge_add_sysctls(sc);
+ if (sc->phyaddr == -1)
+ sc->phyaddr = MGE_READ(sc, MGE_REG_PHYDEV);
+
/* Allocate network interface */
ifp = sc->ifp = if_alloc(IFT_ETHER);
if (ifp == NULL) {
@@ -708,7 +710,7 @@
/* Attach PHY(s) */
error = mii_attach(dev, &sc->miibus, ifp, mge_ifmedia_upd,
- mge_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
+ mge_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY, 0);
if (error) {
device_printf(dev, "attaching PHYs failed\n");
mge_detach(dev);
@@ -717,8 +719,7 @@
sc->mii = device_get_softc(sc->miibus);
/* Tell the MAC where to find the PHY so autoneg works */
- miisc = LIST_FIRST(&sc->mii->mii_phys);
- MGE_WRITE(sc, MGE_REG_PHYDEV, miisc->mii_phy);
+ MGE_WRITE(sc, MGE_REG_PHYDEV, sc->phyaddr);
/* Attach interrupt handlers */
for (i = 0; i < 2; ++i) {
@@ -868,8 +869,7 @@
struct mge_softc *sc = arg;
struct mge_desc_wrapper *dw;
volatile uint32_t reg_val;
- int i, count;
-
+ int i;
MGE_GLOBAL_LOCK_ASSERT(sc);
@@ -949,17 +949,6 @@
reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
reg_val |= PORT_SERIAL_ENABLE;
MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
- count = 0x100000;
- for (;;) {
- reg_val = MGE_READ(sc, MGE_PORT_STATUS);
- if (reg_val & MGE_STATUS_LINKUP)
- break;
- DELAY(100);
- if (--count == 0) {
- if_printf(sc->ifp, "Timeout on link-up\n");
- break;
- }
- }
/* Setup interrupts coalescing */
mge_set_rxic(sc);
@@ -1484,8 +1473,8 @@
MGE_TRANSMIT_LOCK_ASSERT(sc);
- if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
- IFF_DRV_RUNNING)
+ if (IFM_SUBTYPE(sc->mii->mii_media_active) == IFM_NONE ||
+ (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING)
return;
for (;;) {
diff -Nur src/sys/dev/mge/if_mgevar.h src/sys/dev/mge/if_mgevar.h
--- src/sys/dev/mge/if_mgevar.h 2011-05-04 13:45:36.000000000 +0000
+++ src/sys/dev/mge/if_mgevar.h 2011-05-04 13:52:59.000000000 +0000
@@ -103,6 +103,7 @@
uint32_t mge_tx_tok_cnt;
uint16_t mge_mtu;
int mge_ver;
+ int phyaddr;
};
>Release-Note:
>Audit-Trail:
>Unformatted:
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