Beagleboard stuff

[Ben Gray]

Hi Mark,

     I don't think the OMAP4430 techref manual is available on the TI 
website, however you can get it via the Pandaboard site:

<http://www.pandaboard.org/content/resources/omap-device>

     In terms of cache coherency - the OMAP4430 has separate L1 caches 
(32KB inst/32KB data) for each core with a snoop control unit (ARM SCU?) 
which "ensures memory coherency between the two CPUs".


     In regards to the ARMv6/v7 roadmap, have you started work on this? 
I would love to see some of these changes in the tree and can help out 
in some areas, however if you look at the hacks in my pmap.c code for 
armv7 you'll notice that I'm not very experienced in this area of the 
kernel ;-).


Thanks,
Ben.


> On 3/31/2011 10:02 AM, Damjan Marion wrote:
>> Hi Mark,
>>
>> On Mar 31, 2011, at 3:17 PM, Mark Tinguely wrote:
>>> I have been thinking of the ARMv7 / SMP infrastructure.
>>>
>>> http://www.tinguelys.info/mark/freebsd/v7Roadmap.txt
>>>
>>> Disclaimer: recently, I am less sure that all ARMv6 cores can do TEX 
>>> remap.
>>>
>>> To really take advantage of the new ARM features, we need a newer 
>>> compiler. I have an old hacked up early gcc 4.5 snapshot, but it 
>>> does not compile itself. clang does not cross compile and I have not 
>>> tried to compile it under ARM.
>>>
>>> Does the OMAP4 implement the MP extensions? They would simply the 
>>> SMP coherency/TLB operations by not having to perform an IPI
>> OMAP 4 uses standard Cortex-A9 core. Can you take a look into "ARM 
>> DDI 0407" document? It describer MPCore functionality on Cortex-A9 
>> CPUs so it will probably answer your question.
>>
>> Damjan
>
> Last time that I had looked, TI had not released the technical 
> information on the OMAP4 to the general public. I will look again.
>
> The MP core extensions are optional.
>
> Thank-you,
>
> --Mark.
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