ARMv6 support -- was: OMAP3530 - Beagleboard and I2C problems

[Mark Tinguely]

Olivier Houchard wrote:
>> Rafal, and Oliver: I am certain I have the Sheeva cache corruption 
>> problem during cluster i/o identified and a fix.
>>
>>     
>
> So what's going on ?
>
>   
sent off-list.

>> It is exciting to see all this work on the ARM architecture.
>>
>>     
>
> I'm quite excited by the armv6/v7 features, and finally supporting SMP.
> Is your work available somewhere ? We should definitively create an armv6/v7
> branch in P4 or svn.
>
> Regards,
>
> Olivier
>
>   
I have full files of some rough ARMv7 cpufuncs, busdma_machdep.c for 
version 5 and one for version 6/7 (used by semihalf), switch.s, and 
vector floating point routines. Besides the mentioned changes to the 
switch.s file, there are also calls to keep track of the active 
processors for the current process; this is needed for SMP support.

There are also very dated "diff" files that implement atomic routines 
using the new load-exclusive operation and  hooks to support the new 
switch - for example the process active flag. These will have to be 
redone to patch cleanly and to remove the experimental VIPT level one 
support in the pmap_fix_cache() which, IMO, is code bloat with little 
advantages. These are different changes from the VIPT level TWO changes 
that may be needed if the Sheeva's level 2 cache is VIPT.

I also have some readme files that remind me how the ARMv7 pde/ptes 
could be mapped to eliminate the pv_flags fields, save some pages on 
booting, nuances of the OMAP processor, etc.

These files are unlinked but are on my public_html folder on the 
casselton dot net (which will be going away) web server. I am pretty 
sure I have sent the links or files to most of the active individuals in 
the past. I realize that I am a bit more theoretical and more 
revolutionary in my ideas.

--Mark.