CPU Cache and busdma usage in USB

[Stanislav Sedov]

On Mon, 29 Jun 2009 14:14:45 +0200
Hans Petter Selasky <hselasky at c2i.net> mentioned:

> On Monday 29 June 2009 14:10:11 Stanislav Sedov wrote:
> > On Mon, 29 Jun 2009 13:37:41 +0200
> >
> > Hans Petter Selasky <hselasky at c2i.net> mentioned:
> > > USB is currently _updating_ (!!) the PAGE offset part of "vaddr". If
> > > cpu_dcache_inv_range() is called with an address not starting at the
> > > cache line what will the cpu_dcache_inv_range() do? Will it skip to the
> > > next cache line? Or will it completely skip the whole cache sync
> > > operation?!
> >
> > Currently, the address passed to cpu_dcache_inv_range will be rounded up
> > to the cache line boundary and the whole line will be invalidated if the
> > range requested is smaller than 16KiB.  Otherwise, the whole cache will
> > be invalidated.
> 
> That maybe explains it, because USB will require rounding down the address and 
> rounding up the length accordingly, because it uses the 
> "BUS_DMA_KEEP_PG_OFFSET" flag.
>

My apologies, it appears that my wording in previous email was incorrect.  The
current cpu_dcache_inv_range ARM implementation obviously rounds down the
address passed to the cache line boundary and then invalidates all the lines
affected.

-- 
Stanislav Sedov
ST4096-RIPE
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