FreeBSD/arm support for Marvell chips -- please review

[Rafal Jaworowski]

All,
With the recent series of submits in P4's arm-devel branch, I have completed
import of FreeBSD/arm support for three families of Marvell integrated
systems-on-chip built on ARMv5TE-compliant core. Orion support has been around
for a while already, and recently added were extensions for Kirkwood and
Discovery support, new drivers for integrated peripherals and other improvements.

I'd like to merge this with SVN within the coming weeks, so would like to ask
everyone to review the code and let me know about any comments or notes:

1. CPU + SOC specific integrated peripherals
http://p4web.freebsd.org/@md=d&cd=//depot/&c=jjG@//depot/projects/arm/src/sys/arm/mv/?ac=83

2. Other peripherals:
http://p4web.freebsd.org/@md=d&cd=//depot/&c=jjG@//depot/projects/arm/src/sys/dev/mge/?ac=83
http://p4web.freebsd.org/@md=d&cd=//depot/&c=jjG@//depot/projects/arm/src/sys/dev/usb/ehci_mbus.c?ac=22
http://p4web.freebsd.org/@md=d&cd=//depot/&c=jjG@//depot/projects/arm/src/sys/dev/uart/uart_bus_mbus.c?ac=22
http://p4web.freebsd.org/@md=d&cd=//depot/&c=jjG@//depot/projects/arm/src/sys/dev/uart/uart_cpu_mv.c?ac=22


The code is synced with up-to-date CURRENT and has been successfully tested on
the following chips:
  * 88F5182, 88F5281
  * 88F6281
  * MV78100

Supported functionality highlights:
    * EHCI USB 2.0
    * Ethernet
    * GPIO
    * Interrupt controller
    * L1, L2 cache
    * Timers, watchdog, RTC
    * TWSI (I2C)
    * UART

    * Multiuser operation
    * Self-hosted kernel/world builds
    * NFS- or USB-mounted root filesystem

For users reference I have put together an initial howto with examples and
other details: http://wiki.freebsd.org/FreeBSDMarvell

Rafal