progress on the adi pronghorn metro board
John Hay
jhay at meraka.org.za
Thu Mar 22 08:03:39 UTC 2007
Hi Guys,
With this patch I am at the stage where both an Avila 2348-4 and the
ADI Pronghorn Metro boot from the same kernel binary. The "main" stuff
is working, ie. console, ethernet and mini-pci slots. The iic bus on
the Avila is still working. The one for the Pronghorn is configured,
but I must still write a driver for their max6652 temperature/voltage
sensor before I will know if it is really working.
The biggest difference between the 2 boards are in the 16 GPIO pins.
I think there is only 1 pin that have the same function. :-/
So what I did was to create a structure and then have 2 instances of
it, one with Avila values in it and one with Pronghorn values. Then
early in the boot phase, the board type gets detected and a pointer
gets set to the relevant structure. All the drivers then use this
pointer to get the correct values. The efect is that most of the
drivers needs no checks for the different boards.
What I would like to know is, if this approach is acceptable? Should
I use different files to put the stuff in?
My code is not finished yet, but I thought that I would like to get
some feedback. I still have to replace some of the numbers in the
structure with defined values. I would also like to try and really
probe the iic devices and not just assume that they are there.
John
--
John Hay -- John.Hay at meraka.csir.co.za / jhay at FreeBSD.org
Index: avila_led.c
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/avila_led.c,v
retrieving revision 1.1
diff -u -r1.1 avila_led.c
--- avila_led.c 22 Nov 2006 12:57:17 -0000 1.1
+++ avila_led.c 21 Mar 2007 19:04:14 -0000
@@ -66,6 +66,8 @@
static int
led_avila_probe(device_t dev)
{
+ if (ixp425_board->ib_board_type != BOARD_AVILA)
+ return ENXIO;
device_set_desc(dev, "Gateworks Avila GPIO connected LED");
return (0);
}
Index: avila_machdep.c
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/avila_machdep.c,v
retrieving revision 1.3
diff -u -r1.3 avila_machdep.c
--- avila_machdep.c 2 Feb 2007 05:14:21 -0000 1.3
+++ avila_machdep.c 22 Mar 2007 05:42:19 -0000
@@ -260,6 +260,8 @@
extern vm_offset_t xscale_cache_clean_addr;
+static void init_board_type(void);
+
void *
initarm(void *arg, void *arg2)
{
@@ -482,6 +484,7 @@
* Fetch the SDRAM start/size from the ixp425 SDRAM configration
* registers.
*/
+ init_board_type();
cninit();
memsize = ixp425_sdram_size();
physmem = memsize / PAGE_SIZE;
@@ -539,3 +542,70 @@
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
sizeof(struct pcb)));
}
+
+static struct ixp425_board board_avila = {
+ .ib_board_type = BOARD_AVILA,
+ .ib_pci_int_a = IXP425_INT_GPIO_11,
+ .ib_pci_int_b = IXP425_INT_GPIO_10,
+ .ib_pci_int_c = IXP425_INT_GPIO_9,
+ .ib_pci_int_d = IXP425_INT_GPIO_8,
+ .ib_pci_clk_en = -1,
+ .ib_pci_clk = 14 /* GPIO_PCI_CLK */,
+ .ib_pci_reset = 13 /* GPIO_PCI_RESET */,
+ .ib_pci_slot_top = 32,
+ .ib_ata_cs0 = IXP425_EXP_BUS_CS1_HWBASE,
+ .ib_ata_cs0_size = IXP425_EXP_BUS_CS1_SIZE,
+ .ib_ata_cs1 = IXP425_EXP_BUS_CS2_HWBASE,
+ .ib_ata_cs1_size = IXP425_EXP_BUS_CS2_SIZE,
+ .ib_ata_int_pin = 12,
+ .ib_ata_int = IXP425_INT_GPIO_12,
+ .ib_iic_scl = 6 /* GPIO_I2C_SCL */,
+ .ib_iic_sda = 7 /* GPIO_I2C_SDA */,
+ .ib_uartcn_vbase = IXP425_UART0_VBASE,
+ .ib_uartcn_hwbase = IXP425_UART0_HWBASE,
+ .ib_uartcn_int = IXP425_INT_UART0,
+ .ib_uartalt_vbase = IXP425_UART1_VBASE,
+ .ib_uartalt_hwbase = IXP425_UART1_HWBASE,
+ .ib_uartalt_int = IXP425_INT_UART1,
+ .ib_watchdog = -1
+};
+
+static struct ixp425_board board_pronghorn = {
+ .ib_board_type = BOARD_PRONGHORN,
+ .ib_pci_int_a = IXP425_INT_GPIO_4,
+ .ib_pci_int_b = IXP425_INT_GPIO_6,
+ .ib_pci_int_c = IXP425_INT_GPIO_11,
+ .ib_pci_int_d = IXP425_INT_GPIO_1,
+ .ib_pci_clk_en = 3,
+ .ib_pci_clk = 14 /* GPIO_PCI_CLK */,
+ .ib_pci_reset = 12,
+ .ib_pci_slot_top = 20,
+ .ib_ata_cs0 = IXP425_EXP_BUS_CS3_HWBASE,
+ .ib_ata_cs0_size = IXP425_EXP_BUS_CS3_SIZE,
+ .ib_ata_cs1 = IXP425_EXP_BUS_CS4_HWBASE,
+ .ib_ata_cs1_size = IXP425_EXP_BUS_CS4_SIZE,
+ .ib_ata_int_pin = 0,
+ .ib_ata_int = IXP425_INT_GPIO_0,
+ .ib_iic_scl = 10,
+ .ib_iic_sda = 9,
+ .ib_uartcn_vbase = IXP425_UART1_VBASE,
+ .ib_uartcn_hwbase = IXP425_UART1_HWBASE,
+ .ib_uartcn_int = IXP425_INT_UART1,
+ .ib_uartalt_vbase = IXP425_UART0_VBASE,
+ .ib_uartalt_hwbase = IXP425_UART0_HWBASE,
+ .ib_uartalt_int = IXP425_INT_UART0,
+ .ib_watchdog = 13,
+};
+
+struct ixp425_board *ixp425_board;
+
+static void
+init_board_type(void)
+{
+ bootverbose = 1;
+ if (bus_space_read_4(&ixp425_bs_tag, IXP425_EXP_VBASE,
+ EXP_TIMING_CS2_OFFSET) != 0)
+ ixp425_board = &board_avila;
+ else
+ ixp425_board = &board_pronghorn;
+}
Index: ixdp425_pci.c
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/ixdp425_pci.c,v
retrieving revision 1.1
diff -u -r1.1 ixdp425_pci.c
--- ixdp425_pci.c 19 Nov 2006 23:55:23 -0000 1.1
+++ ixdp425_pci.c 21 Mar 2007 19:13:51 -0000
@@ -56,59 +56,76 @@
{
struct ixp425_softc *sc = device_get_softc(device_get_parent(dev));
struct ixppcib_softc *pci_sc = device_get_softc(dev);
- uint32_t reg;
+ uint32_t intn, reg;
/* PCI Reset Assert */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
- reg &= ~(1U << GPIO_PCI_RESET);
- GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg & ~(1U << GPIO_PCI_RESET));
+ reg &= ~(1U << ixp425_board->ib_pci_reset);
+ GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
/* PCI Clock Disable */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
reg &= ~GPCLKR_MUX14;
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg & ~GPCLKR_MUX14);
+ /* The ixp425 do not support 66MHz pci clock. */
+ if (ixp425_board->ib_pci_clk_en != -1) {
+ reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
+ reg &= ~(1U << ixp425_board->ib_pci_clk_en);
+ GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
+ }
+
/*
* set GPIO Direction
* Output: PCI_CLK, PCI_RESET
* Input: PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD
*/
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);
- reg &= ~(1U << GPIO_PCI_CLK);
- reg &= ~(1U << GPIO_PCI_RESET);
- reg |= ((1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
- (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
+ if (ixp425_board->ib_pci_clk_en != -1)
+ reg &= ~(1U << ixp425_board->ib_pci_clk_en);
+ reg &= ~(1U << ixp425_board->ib_pci_clk);
+ reg &= ~(1U << ixp425_board->ib_pci_reset);
+ reg |= ((1U << ixp425_board->ib_pci_int_a) |
+ (1U << ixp425_board->ib_pci_int_b) |
+ (1U << ixp425_board->ib_pci_int_c) |
+ (1U << ixp425_board->ib_pci_int_d));
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);
/*
* Set GPIO interrupt type
* PCI_INT_A, PCI_INTB, PCI_INT_C, PCI_INT_D: Active Low
*/
- reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA));
- reg &= ~GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_MASK);
- reg |= GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_ACT_LOW);
- GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA), reg);
-
- reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB));
- reg &= ~GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_MASK);
- reg |= GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_ACT_LOW);
- GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB), reg);
-
- reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC));
- reg &= ~GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_MASK);
- reg |= GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_ACT_LOW);
- GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC), reg);
-
- reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTD));
- reg &= ~GPIO_TYPE(GPIO_PCI_INTD, GPIO_TYPE_MASK);
- reg |= GPIO_TYPE(GPIO_PCI_INTD, GPIO_TYPE_ACT_LOW);
- GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTD), reg);
+ intn = ixp425_board->ib_pci_int_a;
+ reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(intn));
+ reg &= ~GPIO_TYPE(intn, GPIO_TYPE_MASK);
+ reg |= GPIO_TYPE(intn, GPIO_TYPE_ACT_LOW);
+ GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(intn), reg);
+
+ intn = ixp425_board->ib_pci_int_b;
+ reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(intn));
+ reg &= ~GPIO_TYPE(intn, GPIO_TYPE_MASK);
+ reg |= GPIO_TYPE(intn, GPIO_TYPE_ACT_LOW);
+ GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(intn), reg);
+
+ intn = ixp425_board->ib_pci_int_c;
+ reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(intn));
+ reg &= ~GPIO_TYPE(intn, GPIO_TYPE_MASK);
+ reg |= GPIO_TYPE(intn, GPIO_TYPE_ACT_LOW);
+ GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(intn), reg);
+
+ intn = ixp425_board->ib_pci_int_d;
+ reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(intn));
+ reg &= ~GPIO_TYPE(intn, GPIO_TYPE_MASK);
+ reg |= GPIO_TYPE(intn, GPIO_TYPE_ACT_LOW);
+ GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(intn), reg);
/* clear ISR */
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR,
- (1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
- (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
+ (1U << ixp425_board->ib_pci_int_a) |
+ (1U << ixp425_board->ib_pci_int_b) |
+ (1U << ixp425_board->ib_pci_int_c) |
+ (1U << ixp425_board->ib_pci_int_d));
/* wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */
DELAY(1000);
@@ -119,7 +136,7 @@
/* PCI Clock Enable */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
reg |= GPCLKR_MUX14;
- GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | GPCLKR_MUX14);
+ GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);
/*
* wait 100us to satisfy "minimum reset assertion time from clock stable
@@ -128,14 +145,25 @@
DELAY(100);
/* PCI Reset deassert */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
- reg |= 1U << GPIO_PCI_RESET;
- GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg | (1U << GPIO_PCI_RESET));
+ reg |= 1U << ixp425_board->ib_pci_reset;
+ GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
pci_sc->sc_irq_rman.rm_type = RMAN_ARRAY;
pci_sc->sc_irq_rman.rm_descr = "IXP425 PCI IRQs";
- CTASSERT(PCI_INT_D < PCI_INT_A);
- /* XXX this overlaps the irq's setup in ixp425_attach */
+ /*
+ * XXX this overlaps the irq's setup in ixp425_attach
+ *
+ * PCI irq's on the Pronghorn are not consecutive, so do
+ * them one at a time.
+ */
if (rman_init(&pci_sc->sc_irq_rman) != 0 ||
- rman_manage_region(&pci_sc->sc_irq_rman, PCI_INT_D, PCI_INT_A) != 0)
+ rman_manage_region(&pci_sc->sc_irq_rman,
+ ixp425_board->ib_pci_int_a, ixp425_board->ib_pci_int_a) != 0 ||
+ rman_manage_region(&pci_sc->sc_irq_rman,
+ ixp425_board->ib_pci_int_b, ixp425_board->ib_pci_int_b) != 0 ||
+ rman_manage_region(&pci_sc->sc_irq_rman,
+ ixp425_board->ib_pci_int_c, ixp425_board->ib_pci_int_c) != 0 ||
+ rman_manage_region(&pci_sc->sc_irq_rman,
+ ixp425_board->ib_pci_int_d, ixp425_board->ib_pci_int_d) != 0)
panic("ixp425_md_attach: failed to set up IRQ rman");
}
@@ -145,15 +173,22 @@
int
ixp425_md_route_interrupt(device_t bridge, device_t device, int pin)
{
- static int ixp425_pci_table[IXP425_MAX_DEV][IXP425_MAX_LINE] =
- {
- {PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D},
- {PCI_INT_B, PCI_INT_C, PCI_INT_D, PCI_INT_A},
- {PCI_INT_C, PCI_INT_D, PCI_INT_A, PCI_INT_B},
- {PCI_INT_D, PCI_INT_A, PCI_INT_B, PCI_INT_C},
- };
- int dev;
-
+ static int ixp425_pci_table[IXP425_MAX_DEV][IXP425_MAX_LINE];
+ static int table_filled = 0;
+ int di, dev, li;
+
+ if (table_filled == 0) {
+ ixp425_pci_table[0][0] = ixp425_board->ib_pci_int_a;
+ ixp425_pci_table[0][1] = ixp425_board->ib_pci_int_b;
+ ixp425_pci_table[0][2] = ixp425_board->ib_pci_int_c;
+ ixp425_pci_table[0][3] = ixp425_board->ib_pci_int_d;
+ for (di = 1; di < IXP425_MAX_DEV; di++)
+ for (li = 0; li < IXP425_MAX_LINE; li++)
+ ixp425_pci_table[di][li] =
+ ixp425_pci_table[0][(di + li) %
+ IXP425_MAX_LINE];
+ table_filled = 1;
+ }
dev = pci_get_slot(device);
if (bootverbose)
device_printf(bridge, "routing pin %d for %s\n", pin,
Index: ixp425.c
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/ixp425.c,v
retrieving revision 1.5
diff -u -r1.5 ixp425.c
--- ixp425.c 14 Mar 2007 19:03:07 -0000 1.5
+++ ixp425.c 19 Mar 2007 09:50:59 -0000
@@ -278,9 +278,9 @@
rmanp = &sc->sc_irq_rman;
if (isuart) {
if (device_get_unit(dev) == 0)
- start = IXP425_INT_UART0;
+ start = ixp425_board->ib_uartcn_int;
else
- start = IXP425_INT_UART1;
+ start = ixp425_board->ib_uartalt_int;
end = start;
}
break;
@@ -289,9 +289,9 @@
rmanp = &sc->sc_mem_rman;
if (isuart) {
if (device_get_unit(dev) == 0)
- start = IXP425_UART0_HWBASE;
+ start = ixp425_board->ib_uartcn_hwbase;
else
- start = IXP425_UART1_HWBASE;
+ start = ixp425_board->ib_uartalt_hwbase;
end = start + 0x1000;
}
if (getvbase(start, end - start, &vbase))
@@ -326,9 +326,9 @@
if (flags & INTR_TYPE_TTY) {
/* XXX: wrong. */
if (device_get_unit(dev) == 0)
- rman_set_start(ires, IXP425_INT_UART0);
+ rman_set_start(ires, ixp425_board->ib_uartcn_int);
else
- rman_set_start(ires, IXP425_INT_UART1);
+ rman_set_start(ires, ixp425_board->ib_uartalt_int);
rman_set_end(ires, rman_get_start(ires));
}
BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr,
Index: ixp425_iic.c
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/ixp425_iic.c,v
retrieving revision 1.1
diff -u -r1.1 ixp425_iic.c
--- ixp425_iic.c 19 Nov 2006 23:55:23 -0000 1.1
+++ ixp425_iic.c 21 Mar 2007 17:50:07 -0000
@@ -61,6 +61,8 @@
device_t sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_gpio_ioh;
+ uint32_t sc_scl_bit;
+ uint32_t sc_sda_bit;
device_t iicbb;
};
@@ -85,11 +87,13 @@
sc->sc_dev = dev;
sc->sc_iot = sa->sc_iot;
sc->sc_gpio_ioh = sa->sc_gpio_ioh;
+ sc->sc_scl_bit = 1U << ixp425_board->ib_iic_scl;
+ sc->sc_sda_bit = 1U << ixp425_board->ib_iic_sda;
GPIO_CONF_SET(sc, IXP425_GPIO_GPOER,
- GPIO_I2C_SCL_BIT | GPIO_I2C_SDA_BIT);
+ sc->sc_scl_bit | sc->sc_sda_bit);
GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR,
- GPIO_I2C_SCL_BIT | GPIO_I2C_SDA_BIT);
+ sc->sc_scl_bit | sc->sc_sda_bit);
/* add generic bit-banging code */
if ((sc->iicbb = device_add_child(dev, "iicbb", -1)) == NULL)
@@ -113,10 +117,10 @@
struct ixpiic_softc *sc = ixpiic_sc;
uint32_t reg;
- GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
+ GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, sc->sc_scl_bit);
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR);
- return (reg & GPIO_I2C_SCL_BIT);
+ return (reg & sc->sc_scl_bit);
}
static int
@@ -125,10 +129,10 @@
struct ixpiic_softc *sc = ixpiic_sc;
uint32_t reg;
- GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
+ GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, sc->sc_sda_bit);
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR);
- return (reg & GPIO_I2C_SDA_BIT);
+ return (reg & sc->sc_sda_bit);
}
static void
@@ -136,11 +140,11 @@
{
struct ixpiic_softc *sc = ixpiic_sc;
- GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SDA_BIT);
+ GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, sc->sc_sda_bit);
if (val)
- GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
+ GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, sc->sc_sda_bit);
else
- GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
+ GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, sc->sc_sda_bit);
DELAY(I2C_DELAY);
}
@@ -149,11 +153,11 @@
{
struct ixpiic_softc *sc = ixpiic_sc;
- GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SCL_BIT);
+ GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, sc->sc_scl_bit);
if (val)
- GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
+ GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, sc->sc_scl_bit);
else
- GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
+ GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, sc->sc_scl_bit);
DELAY(I2C_DELAY);
}
Index: ixp425_pci.c
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/ixp425_pci.c,v
retrieving revision 1.4
diff -u -r1.4 ixp425_pci.c
--- ixp425_pci.c 6 Mar 2007 10:58:22 -0000 1.4
+++ ixp425_pci.c 21 Mar 2007 17:18:45 -0000
@@ -355,8 +355,9 @@
slot &= 0x1f;
func &= 0x07;
/* configuration type 0 */
- PCI_CSR_WRITE_4(sc, PCI_NP_AD, (1U << (32 - slot)) |
- (func << 8) | (reg & ~3));
+ PCI_CSR_WRITE_4(sc, PCI_NP_AD,
+ (1U << (ixp425_board->ib_pci_slot_top - slot)) |
+ (func << 8) | (reg & ~3));
}
} else {
/* configuration type 1 */
Index: ixp425var.h
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/ixp425var.h,v
retrieving revision 1.2
diff -u -r1.2 ixp425var.h
--- ixp425var.h 17 Jan 2007 00:58:25 -0000 1.2
+++ ixp425var.h 21 Mar 2007 17:15:57 -0000
@@ -87,8 +87,38 @@
#define GPIO_CONF_READ_4(sc, reg) \
bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, reg)
+struct ixp425_board {
+ int ib_board_type;
+ int ib_pci_int_a;
+ int ib_pci_int_b;
+ int ib_pci_int_c;
+ int ib_pci_int_d;
+ int ib_pci_clk_en;
+ int ib_pci_clk;
+ int ib_pci_reset;
+ int ib_pci_slot_top;
+ int ib_ata_cs0;
+ int ib_ata_cs0_size;
+ int ib_ata_cs1;
+ int ib_ata_cs1_size;
+ int ib_ata_int_pin;
+ int ib_ata_int;
+ int ib_iic_scl;
+ int ib_iic_sda;
+ int ib_uartcn_vbase;
+ int ib_uartcn_hwbase;
+ int ib_uartcn_int;
+ int ib_uartalt_vbase;
+ int ib_uartalt_hwbase;
+ int ib_uartalt_int;
+ int ib_watchdog;
+};
+#define BOARD_AVILA 0
+#define BOARD_PRONGHORN 1
+
extern struct bus_space ixp425_bs_tag;
extern struct bus_space ixp425_a4x_bs_tag;
+extern struct ixp425_board *ixp425_board;
void ixp425_io_bs_init(bus_space_tag_t, void *);
void ixp425_mem_bs_init(bus_space_tag_t, void *);
Index: uart_bus_ixp425.c
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/uart_bus_ixp425.c,v
retrieving revision 1.1
diff -u -r1.1 uart_bus_ixp425.c
--- uart_bus_ixp425.c 19 Nov 2006 23:55:23 -0000 1.1
+++ uart_bus_ixp425.c 19 Mar 2007 17:21:42 -0000
@@ -82,8 +82,9 @@
* just set them here and proceed. But this is fragile...
*/
bus_space_write_4(&ixp425_a4x_bs_tag,
- device_get_unit(dev) == 0 ? IXP425_UART0_VBASE : IXP425_UART1_VBASE,
- IXP425_UART_IER, IXP425_UART_IER_UUE | IXP425_UART_IER_RTOIE);
+ device_get_unit(dev) == 0 ? ixp425_board->ib_uartcn_vbase :
+ ixp425_board->ib_uartalt_vbase, IXP425_UART_IER,
+ IXP425_UART_IER_UUE | IXP425_UART_IER_RTOIE);
return(uart_bus_probe(dev, 0, IXP425_UART_FREQ, 0, 0));
}
Index: uart_cpu_ixp425.c
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/uart_cpu_ixp425.c,v
retrieving revision 1.1
diff -u -r1.1 uart_cpu_ixp425.c
--- uart_cpu_ixp425.c 19 Nov 2006 23:55:23 -0000 1.1
+++ uart_cpu_ixp425.c 19 Mar 2007 17:20:20 -0000
@@ -62,6 +62,6 @@
di->parity = UART_PARITY_NONE;
uart_bus_space_io = &ixp425_a4x_bs_tag;
uart_bus_space_mem = NULL;
- di->bas.bsh = IXP425_UART0_VBASE;
+ di->bas.bsh = ixp425_board->ib_uartcn_vbase;
return (0);
}
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