PEBS support in hwpmc

[Bret Ketchum]

    Looks like PT would assist in instruction execution performance
analysis. PEBS provide information related to uops flows in the OOO
pipeline including cache operations, prefetch, etc.

On Fri, Oct 20, 2017 at 10:50 AM, Ruslan Bukin
<ruslan.bukin at cl.cam.ac.uk> wrote:
> I have not seen that yet. We are working on Intel PT support currently.
> But we plan to look at ARM v8.2 Statistical Profiling Extension technology too, which sounds similar to PEBS by Intel ?
>
> Ruslan
>
> On Fri, Oct 20, 2017 at 06:27:55AM -0500, Bret Ketchum wrote:
>> All,
>>
>>     I apologize if there is a better forum for this question. Is there
>> any current effort to support Processor Event Based Sampling in hwpmc?
>> Without this support (or a VTune subscription) understanding
>> Front-End/Back-End bound applications running on Skylake/Kaby Lake
>> processors will be difficult at best. I'm thinking to simply add a
>> flag and either add a char to iap_event_descr or increase the size of
>> iap_evcode to house the sub-event (EVTSEL). Decoding and reporting the
>> captured PEBS records would need a bit more thought.
>>
>>     Bret
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