bus_dmamap_sync() for bounced client buffers from user address space

[Warner Losh]

> On Apr 29, 2015, at 1:17 PM, Jason Harmening <jason.harmening at gmail.com> wrote:
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> 
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> Yes, that needs to be done regardless of how the pages are wired.  The particular problem here is that some caches on arm and mips are virtually-indexed (usually virtually-indexed, physically-tagged (VIPT)).  That means the flush/invalidate instructions need virtual addresses, so figuring out the correct UVA to use for those could be a challenge.  As I understand it, VIPT caches usually do have some hardware logic for finding all the cachelines that correspond to a physical address, so they can handle multiple VA mappings of the same PA.  But it is unclear to me how cross-processor cache maintenance is supposed to work with VIPT caches on SMP systems.
> 
> If the caches were physically-indexed, then I don't think there would be an issue.  You'd just pass the PA to the flush/invalidate instruction, and presumably a sane SMP implementation would propagate that to other cores via IPI.

I know on MIPS you cannot have more than one mapping to a page you are doing DMA to/from ever.

Warner

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