atomic ops

[Warner Losh]

> On Apr 9, 2015, at 12:14 AM, Mateusz Guzik <mjguzik at gmail.com> wrote:
> 
> On Tue, Oct 28, 2014 at 03:52:22AM +0100, Mateusz Guzik wrote:
> [scratching old content so that I hopefully re-state it nicer]
> 
> I would like to reviwe the discussion about memory barriers provided in
> the kernel.
> 
> The kernel (at least on amd64) lacks lightweight barriers providing only
> following guarantees:
> - all writes are completed prior to given point
> - all reads are completed prior to given point

What does completed mean? That’s a very crappy definition since it
means a range of things.
(1) The CPU has pushed the writes to cache, but the cache is coherent across the whole CPU complex.
(2) The cache has flushed it to the memory controller / PCIe bridge
(3) The memory has actually been updated / The PCIe bridge has pushed the write to the card.
(4) The card has completed its transaction.

Which one is it? What’s its purpose? The efficient implementation requires
the definition be towards the start of the list. Convenient programming of certain
devices, however, requires the end…

Warner

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