Simple #define for cache line size

[Ivan Voras]

Marko Zec wrote:
> On Monday 13 April 2009 23:01:23 Ivan Voras wrote:
>> Robert Watson wrote:
>>> --- i386/include/param.h    (revision 190941)
>>> +++ i386/include/param.h    (working copy)
>>> @@ -74,6 +74,10 @@
>>>  #define ALIGNBYTES    _ALIGNBYTES
>>>  #define ALIGN(p)    _ALIGN(p)
>>>
>>> +#ifndef CACHE_LINE_SIZE
>>> +#define    CACHE_LINE_SIZE    64
>>> +#endif
>> Wouldn't it be better to continue the
>>
>> cpu             I486_CPU
>> cpu             I586_CPU
>> cpu             I686_CPU
>>
>> series of defines in kernel configuration and define alignment per
>> CPU architecture?
> 
> We would have to extend our notion of "CPU architecture" for that to 
> make sense.  For example, Pentium Pro / II CPUs had cache line size of 
> 32 bytes, Intel Netburst CPUs (all Pentium-4 and Xeons of the time) 
> have / had 128 bytes, while Pentium-III, Pentium-M and later Core CPUs 
> have 64 bytes.  They are all I686_CPU in our view.

Yes, because it looks like we stopped tracking them after PPro/II -
AFAIK they are the ones originally designated as i686. Runtime checks
are more certain to be correct but will performance be the same (versus
statically computed offsets)? Some code that should take note of cache
line alignment is very performance sensitive.

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