Where do MSI quirks belong? [patch]

[Andre Oppermann]

John Polstra wrote:
> 
> On Nov 20, 2006, at 9:42 AM, John Baldwin wrote:
> 
>> It's going to be a function of the chipset, as something in the chipset
>> (presumably a Host -> PCI bridge) has to listen for writes to 
>> 0xfeeXXXXXX and
>> convert them into APIC messages.  There are two ways I planned on 
>> doing this:
>>
>> 1) Allow PCI-PCI bridges to be blacklisted, and the pcib_alloc_msi[x]()
>> methods would compare the bridge's device id against a blacklist.  
>> This can
>> matter if you have virtual PCI-PCI bridges that really a HT -> PCI 
>> bridge or
>> the like.
>>
>> 2) Blacklist chipsets in the x86 MD code based on the device ID of the 
>> first
>> Host -> PCI bridge at device 0.0.0.
> 
> I have implemented both of these checks, except that I put #2 into the 
> MI code since I couldn't find any reason to make it x86-specific.  
> Here's the patch.  Does it look OK to you?  It works fine here.

IIRC it is not only a chipset problem but also sometimes how a MSI capable
chipset is wired on the mainboard.  So some probing would have to be done
as well.

-- 
Andre