Small Ivy features: FSGSBASE and SMEP.
kostikbel at gmail.com
Sat Sep 8 18:10:24 UTC 2012
Please find at
the patch which should enable the FSGSBASE and SMEP features
supposedly present in the IvyBridge CPUs.
FSGSBASE are four new instructions available in the 64bit mode only.
They allow to access bases for %fs and %gs without touching MSRs.
This makes it possible to both read and write bases in the user mode,
or in ring 0 with lower overhead.
At the moment, WRFSBASE/WRGSBASE instructions should work, but are
useless since any interrupt or context switch overrides bases with the
values set by the arch syscall. Still, RDFSBASE/RDGSBASE might be useful
for some code and I see no reason not to enable them.
SMEP is the nice feature of the processor which makes it trap if ring
0 tries to execute an instruction from usermode-accessible page. It is
another mitigation for things like calling user-controllable function
pointer in kernel, as well as a protection for NULL function pointer
I am sure that we never execute anything in kernel from user page, but
I did not tested the patch since I have no Ivy machine.
I need your reports about boot on Ivy with patch applied. Please include
the lines from verbose dmesg with CPU Features. In particular, the
'Standard Extended Features' report should appear in output.
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