amd64/85852: Typo in amd64 machine/specialreg.h

Nate Eldredge nge at
Wed Sep 7 16:50:12 PDT 2005

>Number:         85852
>Category:       amd64
>Synopsis:       Typo in amd64 machine/specialreg.h
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    freebsd-amd64
>State:          open
>Class:          sw-bug
>Submitter-Id:   current-users
>Arrival-Date:   Wed Sep 07 23:50:10 GMT 2005
>Originator:     Nate Eldredge
>Release:        FreeBSD 5.4-RELEASE-p6
System: FreeBSD vulcan.lan 5.4-RELEASE-p6 FreeBSD 5.4-RELEASE-p6 #0: Sun Sep  4 02:52:11 PDT 2005     nate at vulcan.lan:/usr/obj/usr/src/sys/VULCAN  amd64
There is a mistake in <machine/specialregs.h> on amd64.  The addresses of
the MSR_MC3_* and MSR_MC4_* machine check registers are reversed.

This would be an issue if somebody implements MCA support someday.  I
have been playing with this a little myself.
Compare <machine/specialregs.h> with AMD's documentation.

--- sys/amd64/include/specialreg.h.orig	Wed Sep  7 13:19:24 2005
+++ sys/amd64/include/specialreg.h	Wed Sep  7 13:20:03 2005
@@ -198,14 +198,14 @@
 #define MSR_MC2_STATUS		0x409
 #define MSR_MC2_ADDR		0x40a
 #define MSR_MC2_MISC		0x40b
-#define MSR_MC4_CTL		0x40c
-#define MSR_MC4_STATUS		0x40d
-#define MSR_MC4_ADDR		0x40e
-#define MSR_MC4_MISC		0x40f
-#define MSR_MC3_CTL		0x410
-#define MSR_MC3_STATUS		0x411
-#define MSR_MC3_ADDR		0x412
-#define MSR_MC3_MISC		0x413
+#define MSR_MC3_CTL		0x40c
+#define MSR_MC3_STATUS		0x40d
+#define MSR_MC3_ADDR		0x40e
+#define MSR_MC3_MISC		0x40f
+#define MSR_MC4_CTL		0x410
+#define MSR_MC4_STATUS		0x411
+#define MSR_MC4_ADDR		0x412
+#define MSR_MC4_MISC		0x413
  * Constants related to MSR's.


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