Some questions about Winchester/Newcastle cores of Athlon64
obrien at freebsd.org
Fri Apr 8 10:51:05 PDT 2005
On Wed, Apr 06, 2005 at 06:00:01PM +0200, O. Hartmann wrote:
> In some discussions I read about some memory controler issues of
> Winchester based Athlon64 cores.
You have to speak specifics not marketing "core" names. I can't even
keep them straight -- few within AMD engineering uses them. What silicon
revision are you interested in? 'C0', 'CG', 'D', or 'E'? What specific
Athlon64 model? Athlon64 939-pin's memory controller is different from
754-pin Athlon64 CPU's.
> The CPU will downgrade to DDR333 if 4 double sided memory modules are
> present in a system.
This is true for 754-pin (single-channel) rev. C0 & CG CPU's. I think
this may be true in some cases for 930-pin. This is simply due to
electrical loading issues.
AMD documents this in publication 26094: BIOS and Kernel Developers
Guild. See 4.1.3 "Maximum DRAM Speed as a Function of Loading".
> I also read about a rumor nVidias nForce4 chipset is capable to handle
> 4 double sided memory modules with a Winchester based CPU core,
If you mean a 939-pin CPU, it doesn't have the problem that the 754-pin
CPU's do as it has a dual-channel memory controller. So each channel is
only driving 2 DIMM's, not 4 on a channel as a 754-pin CPU would.
> but throttling down 1T to 2T access cycles, but remeains in DDR400
See what the AMD document has to say about it.
> Is this also an issue of the Newcastle based CPU cores or is this a bug
> in the Winchester cores?
Aggg, marketing names again. :-/
> The oncoming Venice/San Diego cores of Athlon64 CPUs are said to be
> fixed and capable of driving 4 double sided memory modules.
> Is this weird memory controlling behaviour also an issue on Opteron CPUs?
Opteron's will only accept registered(buffered) memory and thus can drive
a higher electrical load on the memory bus.
-- David (obrien at FreeBSD.org)
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