Page fault on Tyan K8S Pro (S2882) board

[Astrodog]

Isn't CPU0 blocked from memory, while CPU1 makes a request (and has it
fulfilled?)
If not... how'd they manage that? Thats cool as hell. Heh.
--- Harrison Grundy


On Wed, 1 Dec 2004 01:00:24 -0800, David O'Brien <obrien at freebsd.org> wrote:
> On Fri, Nov 26, 2004 at 09:01:03PM -0800, Astrodog wrote:
> > Running 1 DIMM in this kind of setup is
> > shooting yourself in the foot. If CPU #1 requests something through CPU
> > #0, and we're using 1 bank of memory the whole setup..... performance is
> > gonna be crap. Both CPUs will be blocked from processing instructions
> > while the request is fulfilled.
> 
> That is not at all true -- CPU0 is not blocked because CPU1 is accessing
> memory directly attached to CPU0.  The memory controller in an Opteron
> operates independently of the CPU cache unit and central processing unit
> ("core").  All of the the HyperTransport connections (3 of them), the
> memory controller, cache unit (2 for dual-core) all attach together thru
> a cross-bar switch.
> 
> 
> > There are known performance issues with the 4+0 memory config... but
> > they're still good if you use 2 or 4 DIMMs.
> 
> There aren't performance issues with 4+0 memory configurations -- unless
> you also consider it a "performance issue" if one is using DDR333 or
> DDR266 memory vs. DDR400.  CPU1 has a higher latency to memory than CPU0,
> 105ns vs. 70ns; BUT 105ns is still lower than the latency of going thru a
> traditional northbridge.
> 
> So its all a trade off of where you want to be on the performance curve.
> 
> --
> -- David  (obrien at FreeBSD.org)
>