ACPI C3 patch for atheros

[M. Warner Losh]

In message: <41D8C5CF.4020606 at root.org>
            Nate Lawson <nate at root.org> writes:
: M. Warner Losh wrote:
: > 0x41 isn't in the standard config space.  It ends at 0x3f.  Therefore,
: > it won't have a PCIR_ define, since it is device specific.
: 
: Ah, didn't notice that.  It should have an ATH_PCIR define then.
: 
: > : It looks like these config writes in ath_pci_attach() should probably be 
: > : done in the PCI bus but they may be driver-specific.  The saves of 
: > : config space in ath_pci_suspend/resume() are definitely suspect since we 
: > : save/resume all config space now.  See sys/dev/pci/pci.c
: > 
: > No, we don't.  We save only the specific portion of the config space
: > that we know something about.  We also only do the read-write portions
: > of the config space.  Drivers are required to save/restore the device
: > specific portion of pci config space.
: 
: Correct, this is a device-specific config register although the others I 
: pointed out (INTLINE, etc.) are standard and are covered by the PCI bus.

True.  Those are now saved/restored...  I thought you were
specifically talking about this one...

Warner