git: deff1fb3dccb - main - arm64: rockchip: clk: Add MUXRAW macros

[Emmanuel Vadot]

The branch main has been updated by manu:

URL: https://cgit.FreeBSD.org/src/commit/?id=deff1fb3dccb13b6961b1e8595f74a2134e65b93

commit deff1fb3dccb13b6961b1e8595f74a2134e65b93
Author:     Emmanuel Vadot <manu at FreeBSD.org>
AuthorDate: 2021-09-15 16:25:09 +0000
Commit:     Emmanuel Vadot <manu at FreeBSD.org>
CommitDate: 2021-09-15 16:43:07 +0000

    arm64: rockchip: clk: Add MUXRAW macros
    
    Some clocks in the RK3328 SoC (and possibly others) have registers not in
    the CLKSEL_CON range. Add a macros for muxes which lives not in the range
    of CLKSEL_CON which just takes a raw offset.
---
 sys/arm64/rockchip/clk/rk_cru.h | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/sys/arm64/rockchip/clk/rk_cru.h b/sys/arm64/rockchip/clk/rk_cru.h
index 1c749d1d2c87..fc838fc11d19 100644
--- a/sys/arm64/rockchip/clk/rk_cru.h
+++ b/sys/arm64/rockchip/clk/rk_cru.h
@@ -170,7 +170,7 @@
 }
 
 /* Complex clock without divider (multiplexer only). */
-#define MUX(_id, _name, _pn, _f,  _mo, _ms, _mw)			\
+#define MUXRAW(_id, _name, _pn, _f,  _mo, _ms, _mw)			\
 {									\
 	.type = RK_CLK_MUX,						\
 	.clk.mux = &(struct rk_clk_mux_def) {				\
@@ -179,13 +179,16 @@
 		.clkdef.parent_names = _pn,				\
 		.clkdef.parent_cnt = nitems(_pn),			\
 		.clkdef.flags = CLK_NODE_STATIC_STRINGS,		\
-		.offset = CRU_CLKSEL_CON(_mo),				\
+		.offset = _mo,						\
 		.shift = _ms,						\
 		.width = _mw,						\
-		.mux_flags = _f, 			\
+		.mux_flags = _f,					\
 	},								\
 }
 
+#define MUX(_id, _name, _pn, _f,  _mo, _ms, _mw)			\
+	MUXRAW(_id, _name, _pn, _f, CRU_CLKSEL_CON(_mo), _ms, _mw)
+
 /* Complex clock without divider (multiplexer only in GRF). */
 #define MUXGRF(_id, _name, _pn, _f,  _mo, _ms, _mw)			\
 {									\