git: 384ee7cc6e9e - main - [PowerPC] [PowerPCSPE] Fix multiple issues in fpsetmask().

[Brandon Bergren]

The branch main has been updated by bdragon:

URL: https://cgit.FreeBSD.org/src/commit/?id=384ee7cc6e9e4ddc91a6e9e623fcbbe5826bce38

commit 384ee7cc6e9e4ddc91a6e9e623fcbbe5826bce38
Author:     Brandon Bergren <bdragon at FreeBSD.org>
AuthorDate: 2021-03-01 03:06:59 +0000
Commit:     Brandon Bergren <bdragon at FreeBSD.org>
CommitDate: 2021-03-01 03:11:29 +0000

    [PowerPC] [PowerPCSPE] Fix multiple issues in fpsetmask().
    
    Building R on powerpc64 exposed a problem in fpsetmask() whereby we
    were not properly clamping the provided mask to the valid range.
    
    This same issue affects powerpc and powerpcspe.
    
    Properly limit the range of bits that can be set via fpsetmask().
    
    While here, use the correct fp_except_t type instead of fp_rnd_t.
    
    Reported by:    pkubaj, jhibbits (in IRC)
    Sponsored by:   Tag1 Consulting, Inc.
    MFC after:      1 week
---
 lib/libc/powerpc/gen/fpsetmask.c    | 6 +++---
 lib/libc/powerpcspe/gen/fpsetmask.c | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/lib/libc/powerpc/gen/fpsetmask.c b/lib/libc/powerpc/gen/fpsetmask.c
index 4d63552470be..f5d52eec5482 100644
--- a/lib/libc/powerpc/gen/fpsetmask.c
+++ b/lib/libc/powerpc/gen/fpsetmask.c
@@ -43,11 +43,11 @@ fp_except_t
 fpsetmask(fp_except_t mask)
 {
 	u_int64_t fpscr;
-	fp_rnd_t old;
+	fp_except_t old;
 
 	__asm__("mffs %0" : "=f"(fpscr));
-	old = (fp_rnd_t)((fpscr >> 3) & 0x1f);
-	fpscr = (fpscr & 0xffffff07) | (mask << 3);
+	old = (fp_except_t)((fpscr >> 3) & 0x1f);
+	fpscr = (fpscr & 0xffffff07) | ((mask & 0x1f) << 3);
 	__asm__ __volatile("mtfsf 0xff,%0" :: "f"(fpscr));
 	return (old);
 }
diff --git a/lib/libc/powerpcspe/gen/fpsetmask.c b/lib/libc/powerpcspe/gen/fpsetmask.c
index e71b822d6e0b..2f48802d9ca3 100644
--- a/lib/libc/powerpcspe/gen/fpsetmask.c
+++ b/lib/libc/powerpcspe/gen/fpsetmask.c
@@ -42,11 +42,11 @@ fp_except_t
 fpsetmask(fp_except_t mask)
 {
 	uint32_t fpscr;
-	fp_rnd_t old;
+	fp_except_t old;
 
 	__asm__ __volatile("mfspr %0, %1" : "=r"(fpscr) : "K"(SPR_SPEFSCR));
-	old = (fp_rnd_t)((fpscr >> 2) & 0x1f);
-	fpscr = (fpscr & 0xffffff83) | (mask << 2);
+	old = (fp_except_t)((fpscr >> 2) & 0x1f);
+	fpscr = (fpscr & 0xffffff83) | ((mask & 0x1f) << 2);
 	__asm__ __volatile("mtspr %1,%0;isync" :: "r"(fpscr), "K"(SPR_SPEFSCR));
 	return (old);
 }