git: a7b05eb16c9d - main - Sync the arm64 special registers with the Armv8.5 XML
Andrew Turner
andrew at FreeBSD.org
Wed Jul 7 10:39:09 UTC 2021
The branch main has been updated by andrew:
URL: https://cgit.FreeBSD.org/src/commit/?id=a7b05eb16c9d84e1fd59864f5da67d23897ed91c
commit a7b05eb16c9d84e1fd59864f5da67d23897ed91c
Author: Andrew Turner <andrew at FreeBSD.org>
AuthorDate: 2021-07-01 01:14:09 +0000
Commit: Andrew Turner <andrew at FreeBSD.org>
CommitDate: 2021-07-06 20:46:55 +0000
Sync the arm64 special registers with the Armv8.5 XML
Add the missing macros and decode all the fields as described in the
Arm Architecture System Registers XML corresponding to Armv8.5.
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D30983
---
sys/arm64/arm64/identcpu.c | 83 +++++++++++++++++++++++++++++++++++++++-------
sys/arm64/include/armreg.h | 51 +++++++++++++++++++++++++---
2 files changed, 117 insertions(+), 17 deletions(-)
diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
index bae5770b4b04..c2812055dfa9 100644
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -304,9 +304,22 @@ static struct mrs_field id_aa64afr1_fields[] = {
/* ID_AA64DFR0_EL1 */
+static struct mrs_field_value id_aa64dfr0_tracefilt[] = {
+ MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_8_4, "Trace v8.4"),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64dfr0_doublelock[] = {
+ MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_IMPL, "DoubleLock"),
+ MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_NONE, ""),
+ MRS_FIELD_VALUE_END,
+};
+
static struct mrs_field_value id_aa64dfr0_pmsver[] = {
MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_NONE, ""),
- MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_V1, "SPE"),
+ MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE, "SPE"),
+ MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_8_3, "SPE v8.3"),
MRS_FIELD_VALUE_END,
};
@@ -328,7 +341,9 @@ static struct mrs_field_value id_aa64dfr0_brps[] = {
static struct mrs_field_value id_aa64dfr0_pmuver[] = {
MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_NONE, ""),
MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3, "PMUv3"),
- MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_1, "PMUv3+16 bit evtCount"),
+ MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_1, "PMUv3 v8.1"),
+ MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_4, "PMUv3 v8.4"),
+ MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_5, "PMUv3 v8.5"),
MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_IMPL, "IMPL PMU"),
MRS_FIELD_VALUE_END,
};
@@ -343,10 +358,15 @@ static struct mrs_field_value id_aa64dfr0_debugver[] = {
MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8, "Debugv8"),
MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_VHE, "Debugv8_VHE"),
MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_2, "Debugv8.2"),
+ MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_4, "Debugv8.4"),
MRS_FIELD_VALUE_END,
};
static struct mrs_field id_aa64dfr0_fields[] = {
+ MRS_FIELD(ID_AA64DFR0, TraceFilt, false, MRS_EXACT,
+ id_aa64dfr0_tracefilt),
+ MRS_FIELD(ID_AA64DFR0, DoubleLock, false, MRS_EXACT,
+ id_aa64dfr0_doublelock),
MRS_FIELD(ID_AA64DFR0, PMSVer, false, MRS_EXACT, id_aa64dfr0_pmsver),
MRS_FIELD(ID_AA64DFR0, CTX_CMPs, false, MRS_EXACT,
id_aa64dfr0_ctx_cmps),
@@ -361,7 +381,7 @@ static struct mrs_field id_aa64dfr0_fields[] = {
};
-/* ID_AA64DFR1 */
+/* ID_AA64DFR1_EL1 */
static struct mrs_field id_aa64dfr1_fields[] = {
MRS_FIELD_END,
};
@@ -524,12 +544,16 @@ static struct mrs_field_value id_aa64isar1_jscvt[] = {
};
static struct mrs_field_value id_aa64isar1_api[] = {
- MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, API, NONE, IMPL),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_API_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_API_PAC, "API PAC"),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC, "API EPAC"),
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar1_apa[] = {
- MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, APA, NONE, IMPL),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_APA_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_APA_PAC, "APA PAC"),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC, "APA EPAC"),
MRS_FIELD_VALUE_END,
};
@@ -562,8 +586,34 @@ static struct mrs_field id_aa64isar1_fields[] = {
/* ID_AA64MMFR0_EL1 */
+static struct mrs_field_value id_aa64mmfr0_exs[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64mmfr0_tgran4_2[] = {
+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_TGran4, ""),
+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_NONE, "No S2 TGran4"),
+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_IMPL, "S2 TGran4"),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64mmfr0_tgran64_2[] = {
+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_TGran64, ""),
+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_NONE, "No S2 TGran64"),
+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_IMPL, "S2 TGran64"),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64mmfr0_tgran16_2[] = {
+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_TGran16, ""),
+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_NONE, "No S2 TGran16"),
+ MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_IMPL, "S2 TGran16"),
+ MRS_FIELD_VALUE_END,
+};
+
static struct mrs_field_value id_aa64mmfr0_tgran4[] = {
- MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4, NONE, IMPL),
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4,NONE, IMPL),
MRS_FIELD_VALUE_END,
};
@@ -577,7 +627,7 @@ static struct mrs_field_value id_aa64mmfr0_tgran16[] = {
MRS_FIELD_VALUE_END,
};
-static struct mrs_field_value id_aa64mmfr0_bigend_el0[] = {
+static struct mrs_field_value id_aa64mmfr0_bigendel0[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEndEL0, FIXED, MIXED),
MRS_FIELD_VALUE_END,
};
@@ -592,7 +642,7 @@ static struct mrs_field_value id_aa64mmfr0_bigend[] = {
MRS_FIELD_VALUE_END,
};
-static struct mrs_field_value id_aa64mmfr0_asid_bits[] = {
+static struct mrs_field_value id_aa64mmfr0_asidbits[] = {
MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_8, "8bit ASID"),
MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_16, "16bit ASID"),
MRS_FIELD_VALUE_END,
@@ -610,17 +660,24 @@ static struct mrs_field_value id_aa64mmfr0_parange[] = {
};
static struct mrs_field id_aa64mmfr0_fields[] = {
+ MRS_FIELD(ID_AA64MMFR0, ExS, false, MRS_EXACT, id_aa64mmfr0_exs),
+ MRS_FIELD(ID_AA64MMFR0, TGran4_2, false, MRS_EXACT,
+ id_aa64mmfr0_tgran4_2),
+ MRS_FIELD(ID_AA64MMFR0, TGran64_2, false, MRS_EXACT,
+ id_aa64mmfr0_tgran64_2),
+ MRS_FIELD(ID_AA64MMFR0, TGran16_2, false, MRS_EXACT,
+ id_aa64mmfr0_tgran16_2),
MRS_FIELD(ID_AA64MMFR0, TGran4, false, MRS_EXACT, id_aa64mmfr0_tgran4),
MRS_FIELD(ID_AA64MMFR0, TGran64, false, MRS_EXACT,
id_aa64mmfr0_tgran64),
MRS_FIELD(ID_AA64MMFR0, TGran16, false, MRS_EXACT,
id_aa64mmfr0_tgran16),
MRS_FIELD(ID_AA64MMFR0, BigEndEL0, false, MRS_EXACT,
- id_aa64mmfr0_bigend_el0),
+ id_aa64mmfr0_bigendel0),
MRS_FIELD(ID_AA64MMFR0, SNSMem, false, MRS_EXACT, id_aa64mmfr0_snsmem),
MRS_FIELD(ID_AA64MMFR0, BigEnd, false, MRS_EXACT, id_aa64mmfr0_bigend),
MRS_FIELD(ID_AA64MMFR0, ASIDBits, false, MRS_EXACT,
- id_aa64mmfr0_asid_bits),
+ id_aa64mmfr0_asidbits),
MRS_FIELD(ID_AA64MMFR0, PARange, false, MRS_EXACT,
id_aa64mmfr0_parange),
MRS_FIELD_END,
@@ -735,7 +792,8 @@ static struct mrs_field_value id_aa64mmfr2_st[] = {
};
static struct mrs_field_value id_aa64mmfr2_nv[] = {
- MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, NV, NONE, IMPL),
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, NV, NONE, 8_3),
+ MRS_FIELD_VALUE(ID_AA64MMFR2_NV_8_4, "NV v8.4"),
MRS_FIELD_VALUE_END,
};
@@ -835,7 +893,8 @@ static struct mrs_field_value id_aa64pfr0_sve[] = {
static struct mrs_field_value id_aa64pfr0_ras[] = {
MRS_FIELD_VALUE(ID_AA64PFR0_RAS_NONE, ""),
- MRS_FIELD_VALUE(ID_AA64PFR0_RAS_V1, "RASv1"),
+ MRS_FIELD_VALUE(ID_AA64PFR0_RAS_IMPL, "RAS"),
+ MRS_FIELD_VALUE(ID_AA64PFR0_RAS_8_4, "RAS v8.4"),
MRS_FIELD_VALUE_END,
};
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index af6e84e6c772..8a2bbb60f3d0 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -266,6 +266,7 @@
#define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT)
#define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT)
#define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT)
+#define ID_AA64DFR0_DebugVer_8_4 (UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT)
#define ID_AA64DFR0_TraceVer_SHIFT 4
#define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT)
#define ID_AA64DFR0_TraceVer_VAL(x) ((x) & ID_AA64DFR0_TraceVer_MASK)
@@ -277,6 +278,8 @@
#define ID_AA64DFR0_PMUVer_NONE (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT)
#define ID_AA64DFR0_PMUVer_3 (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT)
#define ID_AA64DFR0_PMUVer_3_1 (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT)
+#define ID_AA64DFR0_PMUVer_3_4 (UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT)
+#define ID_AA64DFR0_PMUVer_3_5 (UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT)
#define ID_AA64DFR0_PMUVer_IMPL (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
#define ID_AA64DFR0_BRPs_SHIFT 12
#define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT)
@@ -294,7 +297,18 @@
#define ID_AA64DFR0_PMSVer_MASK (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT)
#define ID_AA64DFR0_PMSVer_VAL(x) ((x) & ID_AA64DFR0_PMSVer_MASK)
#define ID_AA64DFR0_PMSVer_NONE (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT)
-#define ID_AA64DFR0_PMSVer_V1 (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
+#define ID_AA64DFR0_PMSVer_SPE (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
+#define ID_AA64DFR0_PMSVer_SPE_8_3 (UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT)
+#define ID_AA64DFR0_DoubleLock_SHIFT 36
+#define ID_AA64DFR0_DoubleLock_MASK (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
+#define ID_AA64DFR0_DoubleLock_VAL(x) ((x) & ID_AA64DFR0_DoubleLock_MASK)
+#define ID_AA64DFR0_DoubleLock_IMPL (UL(0x0) << ID_AA64DFR0_DoubleLock_SHIFT)
+#define ID_AA64DFR0_DoubleLock_NONE (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
+#define ID_AA64DFR0_TraceFilt_SHIFT 40
+#define ID_AA64DFR0_TraceFilt_MASK (UL(0xf) << ID_AA64DFR0_TraceFilt_SHIFT)
+#define ID_AA64DFR0_TraceFilt_VAL(x) ((x) & ID_AA64DFR0_TraceFilt_MASK)
+#define ID_AA64DFR0_TraceFilt_NONE (UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT)
+#define ID_AA64DFR0_TraceFilt_8_4 (UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT)
/* ID_AA64ISAR0_EL1 */
#define ID_AA64ISAR0_EL1 MRS_REG(3, 0, 0, 6, 0)
@@ -385,12 +399,14 @@
#define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK)
#define ID_AA64ISAR1_APA_NONE (UL(0x0) << ID_AA64ISAR1_APA_SHIFT)
-#define ID_AA64ISAR1_APA_IMPL (UL(0x1) << ID_AA64ISAR1_APA_SHIFT)
+#define ID_AA64ISAR1_APA_PAC (UL(0x1) << ID_AA64ISAR1_APA_SHIFT)
+#define ID_AA64ISAR1_APA_EPAC (UL(0x2) << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_API_SHIFT 8
#define ID_AA64ISAR1_API_MASK (UL(0xf) << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API_VAL(x) ((x) & ID_AA64ISAR1_API_MASK)
#define ID_AA64ISAR1_API_NONE (UL(0x0) << ID_AA64ISAR1_API_SHIFT)
-#define ID_AA64ISAR1_API_IMPL (UL(0x1) << ID_AA64ISAR1_API_SHIFT)
+#define ID_AA64ISAR1_API_PAC (UL(0x1) << ID_AA64ISAR1_API_SHIFT)
+#define ID_AA64ISAR1_API_EPAC (UL(0x2) << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_JSCVT_SHIFT 12
#define ID_AA64ISAR1_JSCVT_MASK (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT)
#define ID_AA64ISAR1_JSCVT_VAL(x) ((x) & ID_AA64ISAR1_JSCVT_MASK)
@@ -495,6 +511,29 @@
#define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK)
#define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT)
#define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
+#define ID_AA64MMFR0_TGran16_2_SHIFT 32
+#define ID_AA64MMFR0_TGran16_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT)
+#define ID_AA64MMFR0_TGran16_2_VAL(x) ((x) & ID_AA64MMFR0_TGran16_2_MASK)
+#define ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT)
+#define ID_AA64MMFR0_TGran16_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT)
+#define ID_AA64MMFR0_TGran16_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT)
+#define ID_AA64MMFR0_TGran64_2_SHIFT 36
+#define ID_AA64MMFR0_TGran64_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT)
+#define ID_AA64MMFR0_TGran64_2_VAL(x) ((x) & ID_AA64MMFR0_TGran64_2_MASK)
+#define ID_AA64MMFR0_TGran64_2_TGran64 (UL(0x0) << ID_AA64MMFR0_TGran64_2_SHIFT)
+#define ID_AA64MMFR0_TGran64_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran64_2_SHIFT)
+#define ID_AA64MMFR0_TGran64_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran64_2_SHIFT)
+#define ID_AA64MMFR0_TGran4_2_SHIFT 40
+#define ID_AA64MMFR0_TGran4_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_2_SHIFT)
+#define ID_AA64MMFR0_TGran4_2_VAL(x) ((x) & ID_AA64MMFR0_TGran4_2_MASK)
+#define ID_AA64MMFR0_TGran4_2_TGran4 (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT)
+#define ID_AA64MMFR0_TGran4_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT)
+#define ID_AA64MMFR0_TGran4_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT)
+#define ID_AA64MMFR0_ExS_SHIFT 44
+#define ID_AA64MMFR0_ExS_MASK (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT)
+#define ID_AA64MMFR0_ExS_VAL(x) ((x) & ID_AA64MMFR0_ExS_MASK)
+#define ID_AA64MMFR0_ExS_ALL (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT)
+#define ID_AA64MMFR0_ExS_IMPL (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT)
/* ID_AA64MMFR1_EL1 */
#define ID_AA64MMFR1_EL1 MRS_REG(3, 0, 0, 7, 1)
@@ -578,7 +617,8 @@
#define ID_AA64MMFR2_NV_MASK (UL(0xf) << ID_AA64MMFR2_NV_SHIFT)
#define ID_AA64MMFR2_NV_VAL(x) ((x) & ID_AA64MMFR2_NV_MASK)
#define ID_AA64MMFR2_NV_NONE (UL(0x0) << ID_AA64MMFR2_NV_SHIFT)
-#define ID_AA64MMFR2_NV_IMPL (UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
+#define ID_AA64MMFR2_NV_8_3 (UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
+#define ID_AA64MMFR2_NV_8_4 (UL(0x2) << ID_AA64MMFR2_NV_SHIFT)
#define ID_AA64MMFR2_ST_SHIFT 28
#define ID_AA64MMFR2_ST_MASK (UL(0xf) << ID_AA64MMFR2_ST_SHIFT)
#define ID_AA64MMFR2_ST_VAL(x) ((x) & ID_AA64MMFR2_ST_MASK)
@@ -668,7 +708,8 @@
#define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK)
#define ID_AA64PFR0_RAS_NONE (UL(0x0) << ID_AA64PFR0_RAS_SHIFT)
-#define ID_AA64PFR0_RAS_V1 (UL(0x1) << ID_AA64PFR0_RAS_SHIFT)
+#define ID_AA64PFR0_RAS_IMPL (UL(0x1) << ID_AA64PFR0_RAS_SHIFT)
+#define ID_AA64PFR0_RAS_8_4 (UL(0x2) << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_SVE_SHIFT 32
#define ID_AA64PFR0_SVE_MASK (UL(0xf) << ID_AA64PFR0_SVE_SHIFT)
#define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK)
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