git: 2e50ba70742b - stable/13 - hwpmc: disable uncore class on Sandy Bridge and newer

[Mitchell Horne]

The branch stable/13 has been updated by mhorne:

URL: https://cgit.FreeBSD.org/src/commit/?id=2e50ba70742bac34f144832ceb5f6816fcc06be2

commit 2e50ba70742bac34f144832ceb5f6816fcc06be2
Author:     Mitchell Horne <mhorne at FreeBSD.org>
AuthorDate: 2021-08-04 17:31:36 +0000
Commit:     Mitchell Horne <mhorne at FreeBSD.org>
CommitDate: 2021-08-11 16:49:44 +0000

    hwpmc: disable uncore class on Sandy Bridge and newer
    
    It was written for Nehalem and Westmere, with minor but incomplete
    updates for Sandy Bridge in 78d763a29b15. The uncore architecture
    changed significantly with this generation, bringing new layouts and
    locations for some MSRs.
    
    Misprogramming these MSRs in ucp_start_pmc() may panic the system, and
    this is trivially reproducible via pmcstat(8) on at least Broadwell and
    Haswell. Disable the class on these CPUs until it can be updated more
    completely and leave a TODO comment detailing some of the work required.
    Note that the nclasses value for Broadwell was already incorrect and
    doesn't need changing.
    
    The result is that any uncore events listed by pmcstat -L will no longer
    be allocatable, but this is already the case for newer generations of
    Intel CPUs.
    
    PR:             253687
    Reported by:    Zhenlei Huang <zlei.huang at gmail.com>
    Reviewed by:    kib
    MFC after:      1 week
    Sponsored by:   The FreeBSD Foundation
    Differential Revision:  https://reviews.freebsd.org/D31389
    
    (cherry picked from commit 4f35e8cba232d9256ab1399b8adfb761988e5eff)
---
 sys/dev/hwpmc/hwpmc_intel.c | 31 +++++++++++++++++++++++++------
 1 file changed, 25 insertions(+), 6 deletions(-)

diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c
index aec037b64938..02b8fd9431d1 100644
--- a/sys/dev/hwpmc/hwpmc_intel.c
+++ b/sys/dev/hwpmc/hwpmc_intel.c
@@ -149,7 +149,7 @@ pmc_intel_initialize(void)
 			break;
 		case 0x2A:	/* Per Intel document 253669-039US 05/2011. */
 			cputype = PMC_CPU_INTEL_SANDYBRIDGE;
-			nclasses = 5;
+			nclasses = 3;
 			break;
 		case 0x2D:	/* Per Intel document 253669-044US 08/2012. */
 			cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
@@ -195,7 +195,7 @@ pmc_intel_initialize(void)
 		case 0x3C:	/* Per Intel document 325462-045US 01/2013. */
 		case 0x45:	/* Per Intel document 325462-045US 09/2014. */
 			cputype = PMC_CPU_INTEL_HASWELL;
-			nclasses = 5;
+			nclasses = 3;
 			break;
 		case 0x37:
 		case 0x4A:
@@ -275,10 +275,27 @@ pmc_intel_initialize(void)
 		 * Intel Corei7 and Westmere processors.
 		 */
 	case PMC_CPU_INTEL_COREI7:
-	case PMC_CPU_INTEL_HASWELL:
-	case PMC_CPU_INTEL_SANDYBRIDGE:
 	case PMC_CPU_INTEL_WESTMERE:
+#ifdef notyet
+	/*
+	 * TODO: re-enable uncore class on these processors.
+	 *
+	 * The uncore unit was reworked beginning with Sandy Bridge, including
+	 * the MSRs required to program it. In particular, we need to:
+	 *  - Parse the MSR_UNC_CBO_CONFIG MSR for number of C-box units in the
+	 *    system
+	 *  - Support reading and writing to ARB and C-box units, depending on
+	 *    the requested event
+	 *  - Create some kind of mapping between C-box <--> CPU
+	 *
+	 * Also TODO: support other later changes to these interfaces, to
+	 * enable the uncore class on generations newer than Broadwell.
+	 * Skylake+ appears to use newer addresses for the uncore MSRs.
+	 */
+	case PMC_CPU_INTEL_HASWELL:
 	case PMC_CPU_INTEL_BROADWELL:
+	case PMC_CPU_INTEL_SANDYBRIDGE:
+#endif
 		error = pmc_uncore_initialize(pmc_mdep, ncpus);
 		break;
 	default:
@@ -329,11 +346,13 @@ pmc_intel_finalize(struct pmc_mdep *md)
 	 * Uncore.
 	 */
 	switch (md->pmd_cputype) {
-	case PMC_CPU_INTEL_BROADWELL:
 	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_WESTMERE:
+#ifdef notyet
 	case PMC_CPU_INTEL_HASWELL:
+	case PMC_CPU_INTEL_BROADWELL:
 	case PMC_CPU_INTEL_SANDYBRIDGE:
-	case PMC_CPU_INTEL_WESTMERE:
+#endif
 		pmc_uncore_finalize(md);
 		break;
 	default: