git: dfb9884fac3c - main - cad/verilator: Backport of fix of missing #include <array> bug.

[Yuri Victorovich]

The branch main has been updated by yuri:

URL: https://cgit.FreeBSD.org/ports/commit/?id=dfb9884fac3cec32a9e07eb44e7fea507cc5537d

commit dfb9884fac3cec32a9e07eb44e7fea507cc5537d
Author:     Yuri Victorovich <yuri at FreeBSD.org>
AuthorDate: 2021-06-07 20:38:43 +0000
Commit:     Yuri Victorovich <yuri at FreeBSD.org>
CommitDate: 2021-06-07 20:41:13 +0000

    cad/verilator: Backport of fix of missing #include <array> bug.
---
 cad/verilator/Makefile | 4 ++++
 cad/verilator/distinfo | 4 +++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile
index 0266b72d107f..aa524a1009ce 100644
--- a/cad/verilator/Makefile
+++ b/cad/verilator/Makefile
@@ -1,8 +1,12 @@
 PORTNAME=	verilator
 DISTVERSION=	4.202
+PORTREVISION=	1
 CATEGORIES=	cad
 MASTER_SITES=	https://www.veripool.org/ftp/
 
+PATCH_SITES=	https://github.com/verilator/verilator/commit/
+PATCHFILES=	0f7ec6c9ba52160573df8a7ee90bcc38c837eee7.patch:-p1 # fix for missing #include <array>
+
 MAINTAINER=	yuri at FreeBSD.org
 COMMENT=	Synthesizable Verilog to C++ compiler
 
diff --git a/cad/verilator/distinfo b/cad/verilator/distinfo
index 88185a232daf..1356961c5597 100644
--- a/cad/verilator/distinfo
+++ b/cad/verilator/distinfo
@@ -1,3 +1,5 @@
-TIMESTAMP = 1619289746
+TIMESTAMP = 1623092835
 SHA256 (verilator-4.202.tgz) = d8daff2461493439889f85e4a9ccb2d865e9c4ca1a06f611fe36d64bc020b679
 SIZE (verilator-4.202.tgz) = 3149226
+SHA256 (0f7ec6c9ba52160573df8a7ee90bcc38c837eee7.patch) = bd4f4a7460db08bb2e79b575e289555c4249106e6b3cb9c18c59ca303f8179ac
+SIZE (0f7ec6c9ba52160573df8a7ee90bcc38c837eee7.patch) = 575