cvs commit: src/sys/amd64/amd64 intr_machdep.c io_apic.c local_apic.c mp_machdep.c src/sys/amd64/include apicvar.h intr_machdep.h src/sys/amd64/isa atpic.c src/sys/i386/i386 intr_machdep.c io_apic.c local_apic.c mp_machdep.c ...

[John Baldwin]

jhb         2006-02-28 22:24:55 UTC

  FreeBSD src repository

  Modified files:
    sys/amd64/amd64      intr_machdep.c io_apic.c local_apic.c 
                         mp_machdep.c 
    sys/amd64/include    apicvar.h intr_machdep.h 
    sys/amd64/isa        atpic.c 
    sys/i386/i386        intr_machdep.c io_apic.c local_apic.c 
                         mp_machdep.c 
    sys/i386/include     apicvar.h intr_machdep.h 
    sys/i386/isa         atpic.c 
  Log:
  Rework how we wire up interrupt sources to CPUs:
  - Throw out all of the logical APIC ID stuff.  The Intel docs are somewhat
    ambiguous, but it seems that the "flat" cluster model we are currently
    using is only supported on Pentium and P6 family CPUs.  The other
    "hierarchy" cluster model that is supported on all Intel CPUs with
    local APICs is severely underdocumented.  For example, it's not clear
    if the OS needs to glean the topology of the APIC hierarchy from
    somewhere (neither ACPI nor MP Table include it) and setup the logical
    clusters based on the physical hierarchy or not.  Not only that, but on
    certain Intel chipsets, even though there were 4 CPUs in a logical
    cluster, all the interrupts were only sent to one CPU anyway.
  - We now bind interrupts to individual CPUs using physical addressing via
    the local APIC IDs.  This code has also moved out of the ioapic PIC
    driver and into the common interrupt source code so that it can be
    shared with MSI interrupt sources since MSI is addressed to APICs the
    same way that I/O APIC pins are.
  - Interrupt source classes grow a new method pic_assign_cpu() to bind an
    interrupt source to a specific local APIC ID.
  - The SMP code now tells the interrupt code which CPUs are avaiable to
    handle interrupts in a simpler and more intuitive manner.  For one thing,
    it means we could now choose to not route interrupts to HT cores if we
    wanted to (this code is currently in place in fact, but under an #if 0
    for now).
  - For now we simply do static round-robin of IRQs to CPUs when the first
    interrupt handler just as before, with the change that IRQs are now
    bound to individual CPUs rather than groups of up to 4 CPUs.
  - Because the IRQ to CPU mapping has now been moved up a layer, it would
    be easier to manage this mapping from higher levels.  For example, we
    could allow drivers to specify a CPU affinity map for their interrupts,
    or we could allow a userland tool to bind IRQs to specific CPUs.
  
  The MFC is tentative, but I want to see if this fixes problems some folks
  had with UP APIC kernels on 6.0 on SMP machines (an SMP kernel would work
  fine, but a UP APIC kernel (such as GENERIC in RELENG_6) would lose
  interrupts).
  
  MFC after:      1 week
  
  Revision  Changes    Path
  1.19      +91 -1     src/sys/amd64/amd64/intr_machdep.c
  1.21      +20 -95    src/sys/amd64/amd64/io_apic.c
  1.24      +2 -14     src/sys/amd64/amd64/local_apic.c
  1.269     +18 -22    src/sys/amd64/amd64/mp_machdep.c
  1.17      +0 -1      src/sys/amd64/include/apicvar.h
  1.9       +7 -0      src/sys/amd64/include/intr_machdep.h
  1.19      +14 -2     src/sys/amd64/isa/atpic.c
  1.18      +91 -1     src/sys/i386/i386/intr_machdep.c
  1.26      +20 -95    src/sys/i386/i386/io_apic.c
  1.26      +2 -14     src/sys/i386/i386/local_apic.c
  1.263     +18 -22    src/sys/i386/i386/mp_machdep.c
  1.17      +0 -1      src/sys/i386/include/apicvar.h
  1.11      +7 -0      src/sys/i386/include/intr_machdep.h
  1.25      +14 -2     src/sys/i386/isa/atpic.c