cvs commit: src/sys/net if.c
gavin.atkinson at ury.york.ac.uk
Mon Sep 27 03:10:46 PDT 2004
On Mon, 2004-09-27 at 10:31, Peter Jeremy wrote:
> On Mon, 2004-Sep-27 12:43:29 +0930, Daniel O'Connor wrote:
> >Hmm, MS have a circuit diagram ->
> I bumped into that as well. The innards of the PAL aren't documented
> anywhere that I could see and there seems to be quite a lot of logic
> when the only inputs are the PCI clock and the NMI switch. (Bloated
> design and undocumented internals - sounds familiar :-).
> >Pin 42 is #SERR and the other side of it in ground.
> Does anyone with knowledge of the PCI spec know if just shorting #SERR
> to ground will work? (Assuming that the BIOS/chipset maps #SERR to NMI).
It is possible. The PCI 2.2 spec (section 220.127.116.11) says that it should
be asserted for a *single* clock cycle, then tri-stated. However, it
also suggests that all that is actually necessary is for it to be
sampled as being de-asserted for two successive rising clock edges after
an assertion for an NMI to actually be triggered.
So it depends on how strictly they enforce the need for assertion to
last a "single clock cycle".
Regardless of anything else, I wouldn't like to just short SERR# to
ground with a screwdriver as used to be possible in the Good Ol' ISA
Days... A bit of debounce logic (which I suspect is mainly what the PAL
is there to achieve in the Microsoft design) would be necessary to
prevent multiple NMI's from being sent.
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