cvs commit: ports/cad/p5-Verilog-Perl Makefile distinfo

[Andrej Zverev]

az          2009-08-24 06:01:24 UTC

  FreeBSD ports repository

  Modified files:
    cad/p5-Verilog-Perl  Makefile distinfo 
  Log:
  Update to 2.213
  
  PR:     ports/138081
  Submitted by:   tacilio.net at ee.ufcg.edu.br (maintainer)
  
  Revision  Changes    Path
  1.4       +1 -1      ports/cad/p5-Verilog-Perl/Makefile
  1.3       +3 -3      ports/cad/p5-Verilog-Perl/distinfo