5.1.0pre4 work du jour

[Doug Ledford]

Justin T. Gibbs wrote:
> 
> > Notice that as soon as the sequencer gets back to being in a valid address
> > range, we re-enable the error detection logic on the chip.  IMNSHO, to leave
> > it disabled would be like having ECC DRAM and telling the motherboard to
> > ignore it because you are getting parity errors.  Is there an actual reason
> > for this code being that way in your driver Justin?
> 
> In my own tests, I found that the chip only seemed to reset it's error
> state after having executed or seen valid data in it's instruction ram.
> This does not seem to occur until you actually restart the sequencer.  In
> the FreeBSD code, we clear the FAILDIS flag as soon as we perform our bus
> reset which occurs just a few ms later.

Ahh, see, our bus reset is before we load the sequencer.  The only thing
left after loading the sequencer is the unpause_sequencer and return.  So,
as you pointed out, there is a problem if you don't at least leave FAILDIS
set until you execute the first instruction, what I'm doing now is to leave
it until the restart_sequencer is called, which now clears all of the
various options out of SEQCTL again.  The one thing I didn't do is use the
SEQRESET bit since I wasn't positive that was universally the same (I still
don't have aic777x docs, just the 78xx docs) and my 2842 was giving me
problems.  I ended up leaving it as three outb instructions, two to set the
address and one to set SEQCTL to FASTMODE only.

-- 

 Doug Ledford  <dledford at dialnet.net>
  Opinions expressed are my own, but
     they should be everybody's.

To Unsubscribe: send mail to majordomo at FreeBSD.org
with "unsubscribe aic7xxx" in the body of the message