2.0.35 and aic7xxx

[Robert G. Brown]

On Mon, 20 Jul 1998, Patrick W. Bryant wrote:

> Whoops.  Now I get 
> 
> (scsi0) BIOS enabled, IO Port 0xfc00, IRQ 10
> (scsi0) IO Memory at 0xf9fff000, MMAP Memory at 0x8809000
> (scsi0) Resetting channel
> (scsi0) Downloading sequencer code... 407 instructions downloaded
> (scsi0:-1:-1:-1) Data Parity Efforo during PCI address or PCI writephase.
> (scsi0:-1:-1:-1) Received a PCI Target Abort
> 
> then the rest (included below).  Sorry if my oversight caused any
> goose-chasing.

Not on my part:-) Interesting.  You are getting much farther in the
setup process than I am right now, but we are both bombing on the Data
Parity Error message.  I'm dying currently in the aic7xxx_detect
routine, I'm pretty sure.  I'm about to try a hacked aic7xxx.o with
printk's around every major step to see where it might be occurring --
my bet is on the devconfig write, since that seems to be parity
sensitive (at least, there is a parity conditional associated with it).

You have a system with both 7860 and 7890 onboard as well, right?  I
wonder if having a split dual onboard controler is screwing up the
aic7xxx initialization routines...

   rgb

Robert G. Brown	                       http://www.phy.duke.edu/~rgb/
Duke University Dept. of Physics, Box 90305
Durham, N.C. 27708-0305
Phone: 1-919-660-2567  Fax: 919-660-2525     email:rgb at phy.duke.edu




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