From nobody Sun Sep 11 04:05:28 2022 X-Original-To: pkg-fallout@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4MQGNT5R7cz4bpLh for ; Sun, 11 Sep 2022 04:05:29 +0000 (UTC) (envelope-from pkg-fallout@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4MQGNT0rn9z3DZn; Sun, 11 Sep 2022 04:05:29 +0000 (UTC) (envelope-from pkg-fallout@FreeBSD.org) Received: from beefy18.nyi.freebsd.org (beefy18.nyi.freebsd.org [IPv6:2610:1c1:1:6080::16:21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4MQGNS5k4SzX9J; Sun, 11 Sep 2022 04:05:28 +0000 (UTC) (envelope-from pkg-fallout@FreeBSD.org) Received: from beefy18.nyi.freebsd.org (localhost [127.0.0.1]) by beefy18.nyi.freebsd.org (8.16.1/8.16.1) with ESMTP id 28B45Sv7061408; Sun, 11 Sep 2022 04:05:28 GMT (envelope-from pkg-fallout@FreeBSD.org) Received: (from root@localhost) by beefy18.nyi.freebsd.org (8.16.1/8.16.1/Submit) id 28B45SH9061407; Sun, 11 Sep 2022 04:05:28 GMT (envelope-from pkg-fallout@FreeBSD.org) Date: Sun, 11 Sep 2022 04:05:28 GMT From: pkg-fallout@FreeBSD.org Message-Id: <202209110405.28B45SH9061407@beefy18.nyi.freebsd.org> To: manu@FreeBSD.org Subject: [package - main-amd64-default][devel/lattice-ice40-examples-hx1k] Failed for lattice-ice40-examples-hx1k-g20180310_1 in build Cc: pkg-fallout@FreeBSD.org ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1662869129; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc; bh=cjl8PcfjSIfyrEWTX1ODaohhE2SPA3Rc+Q8gf0Sbge0=; b=LJJjsjVy4gPMkQ/hWqrm6zh00/E4p2HEIO+ZiwOouLWWYY/uyN3h9qBQHrIcLLertnAlkz C6pKEfOpl9F6u3IUZf93wCLO+fMrFZHi3Kc8IIeRPAxzxY+9rrHVLixIWrQ2XOgHwJVCgs tQ9ApnqCpkEANKScS6TxSe0dRbR227YPEJfc+UnGYfLfJmKQmo1f67FSnmDqkUC2j41Zur gSUkLU5rf+hP7vc2cs2JYZd/Mr9rEPgdc0IpwnMPNIhPOFZKIk6Cbdp2JPuv2vMM5KS+7P c+/Ts+KIHBwiq3NzgvOAjPtxT7rxofuHh50SbUf2vgPbVkTrz3RI74Q/y2XQ7A== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1662869129; a=rsa-sha256; cv=none; b=J95CZ046CyinX90nGuJt1ESGOm/b2/EX6yvlt68MWemj0GJUSG0flLpDk45W4QdKv6e1sj igmCwI/WyYYduF0sUpKS+GGgDr17DR3HMeWloRQr+ACJ+07JMmPU0FwPitxe/Vd+56ff/T HGDqqhRCBQS4PeuKS0M41+6Ie4nK6t5hUlmoFKKyr0QuesaEtSHn46Qt/mOunuJo+OivIw zOwrIbnt/W8vdKbf9DoYB1hZv26E61/dgnpCctmcfvpuBVn3+wdEwWwlKCKzAUBcCIhmKf if5j7nLDlXAjQd3MLmkuzkCrUrFwjvSGrEf+FMo0H4TUpGrLydhILEj4ZxHwaA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N List-Id: Fallout logs from package building List-Archive: https://lists.freebsd.org/archives/freebsd-pkg-fallout List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-pkg-fallout@freebsd.org You are receiving this mail as a port that you maintain is failing to build on the FreeBSD package build server. Please investigate the failure and submit a PR to fix build. Maintainer: manu@FreeBSD.org Log URL: http://beefy18.nyi.freebsd.org/data/main-amd64-default/p23c196516a66_s45ad955714/logs/lattice-ice40-examples-hx1k-g20180310_1.log Build URL: http://beefy18.nyi.freebsd.org/build.html?mastername=main-amd64-default&build=p23c196516a66_s45ad955714 Log: =>> Building devel/lattice-ice40-examples-hx1k build started at Sun Sep 11 04:05:13 UTC 2022 port directory: /usr/ports/devel/lattice-ice40-examples-hx1k package name: lattice-ice40-examples-hx1k-g20180310_1 building for: FreeBSD main-amd64-default-job-04 14.0-CURRENT FreeBSD 14.0-CURRENT 1400067 amd64 maintained by: manu@FreeBSD.org Makefile ident: Poudriere version: 3.2.8-21-g883afb07 Host OSVERSION: 1400063 Jail OSVERSION: 1400067 Job Id: 04 !!! Jail is newer than host. (Jail: 1400067, Host: 1400063) !!! !!! This is not supported. !!! !!! Host kernel must be same or newer than jail. !!! !!! Expect build failures. !!! ---Begin Environment--- SHELL=/bin/sh OSVERSION=1400067 UNAME_v=FreeBSD 14.0-CURRENT 1400067 UNAME_r=14.0-CURRENT BLOCKSIZE=K MAIL=/var/mail/root MM_CHARSET=UTF-8 LANG=C.UTF-8 STATUS=1 HOME=/root PATH=/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/root/bin LOCALBASE=/usr/local USER=root LIBEXECPREFIX=/usr/local/libexec/poudriere POUDRIERE_VERSION=3.2.8-21-g883afb07 MASTERMNT=/usr/local/poudriere/data/.m/main-amd64-default/ref POUDRIERE_BUILD_TYPE=bulk PACKAGE_BUILDING=yes SAVED_TERM= PWD=/usr/local/poudriere/data/.m/main-amd64-default/ref/.p/pool P_PORTS_FEATURES=FLAVORS SELECTED_OPTIONS MASTERNAME=main-amd64-default SCRIPTPREFIX=/usr/local/share/poudriere OLDPWD=/usr/local/poudriere/data/.m/main-amd64-default/ref/.p SCRIPTPATH=/usr/local/share/poudriere/bulk.sh POUDRIEREPATH=/usr/local/bin/poudriere ---End Environment--- ---Begin Poudriere Port Flags/Env--- PORT_FLAGS= PKGENV= FLAVOR= DEPENDS_ARGS= MAKE_ARGS= ---End Poudriere Port Flags/Env--- ---Begin OPTIONS List--- ---End OPTIONS List--- --MAINTAINER-- manu@FreeBSD.org --End MAINTAINER-- --CONFIGURE_ARGS-- --End CONFIGURE_ARGS-- --CONFIGURE_ENV-- MAKE=gmake XDG_DATA_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work XDG_CONFIG_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work XDG_CACHE_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.cache HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work TMPDIR="/tmp" PATH=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/root/bin PKG_CONFIG_LIBDIR=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.pkgconfig:/usr/local/libdata/pkgconfig:/usr/local/share/pkgconfig:/usr/libdata/pkgconfig SHELL=/bin/sh CONFIG_SHELL=/bin/sh --End CONFIGURE_ENV-- --MAKE_ENV-- XDG_DATA_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work XDG_CONFIG_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work XDG_CACHE_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.cache HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work TMPDIR="/tmp" PATH=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/root/bin PKG_CONFIG_LIBDIR=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.pkgconfig:/usr/local/libdata/pkgconfig:/usr/local/share/pkgconfig:/usr/libdata/pkgconfig NO_PIE=yes MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES PREFIX=/usr/local LOCALBASE=/usr/local CC="cc" CFLAGS="-O2 -pipe -fstack-protector-strong -fno-strict-aliasing " CPP="cpp" CPPFLAGS="" LDFLAGS=" -fstack-protector-strong " LIBS="" CXX="c++" CXXFLAGS="-O2 -pipe -fstack-protector-strong -fno-strict-aliasing " MANPREFIX="/usr/local" BSD_INSTALL_PROGRAM="i nstall -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" --End MAKE_ENV-- --PLIST_SUB-- OSREL=14.0 PREFIX=%D LOCALBASE=/usr/local RESETPREFIX=/usr/local LIB32DIR=lib DOCSDIR="share/doc/lattice-ice40-examples-hx1k" EXAMPLESDIR="share/examples/lattice-ice40-olimex" DATADIR="share/lattice-ice40-examples-hx1k" WWWDIR="www/lattice-ice40-examples-hx1k" ETCDIR="etc/lattice-ice40-examples-hx1k" --End PLIST_SUB-- --SUB_LIST-- PREFIX=/usr/local LOCALBASE=/usr/local DATADIR=/usr/local/share/lattice-ice40-examples-hx1k DOCSDIR=/usr/local/share/doc/lattice-ice40-examples-hx1k EXAMPLESDIR=/usr/local/share/examples/lattice-ice40-olimex WWWDIR=/usr/local/www/lattice-ice40-examples-hx1k ETCDIR=/usr/local/etc/lattice-ice40-examples-hx1k --End SUB_LIST-- ---Begin make.conf--- USE_PACKAGE_DEPENDS=yes BATCH=yes WRKDIRPREFIX=/wrkdirs PORTSDIR=/usr/ports PACKAGES=/packages DISTDIR=/distfiles PACKAGE_BUILDING=yes PACKAGE_BUILDING_FLAVORS=yes #### /usr/local/etc/poudriere.d/make.conf #### # XXX: We really need this but cannot use it while 'make checksum' does not # try the next mirror on checksum failure. It currently retries the same # failed mirror and then fails rather then trying another. It *does* # try the next if the size is mismatched though. #MASTER_SITE_FREEBSD=yes # Build ALLOW_MAKE_JOBS_PACKAGES with 2 jobs MAKE_JOBS_NUMBER=2 #### /usr/ports/Mk/Scripts/ports_env.sh #### _CCVERSION_921dbbb2=FreeBSD clang version 14.0.5 (https://github.com/llvm/llvm-project.git llvmorg-14.0.5-0-gc12386ae247c) Target: x86_64-unknown-freebsd14.0 Thread model: posix InstalledDir: /usr/bin _ALTCCVERSION_921dbbb2=none _CXXINTERNAL_acaad9ca=FreeBSD clang version 14.0.5 (https://github.com/llvm/llvm-project.git llvmorg-14.0.5-0-gc12386ae247c) Target: x86_64-unknown-freebsd14.0 Thread model: posix InstalledDir: /usr/bin "/usr/bin/ld" "--eh-frame-hdr" "-dynamic-linker" "/libexec/ld-elf.so.1" "--hash-style=both" "--enable-new-dtags" "-o" "a.out" "/usr/lib/crt1.o" "/usr/lib/crti.o" "/usr/lib/crtbegin.o" "-L/usr/lib" "/dev/null" "-lc++" "-lm" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" "/usr/lib/crtend.o" "/usr/lib/crtn.o" CC_OUTPUT_921dbbb2_58173849=yes CC_OUTPUT_921dbbb2_9bdba57c=yes CC_OUTPUT_921dbbb2_6a4fe7f5=yes CC_OUTPUT_921dbbb2_6bcac02b=yes CC_OUTPUT_921dbbb2_67d20829=yes CC_OUTPUT_921dbbb2_bfa62e83=yes CC_OUTPUT_921dbbb2_f0b4d593=yes CC_OUTPUT_921dbbb2_308abb44=yes CC_OUTPUT_921dbbb2_f00456e5=yes CC_OUTPUT_921dbbb2_65ad290d=yes CC_OUTPUT_921dbbb2_f2776b26=yes CC_OUTPUT_921dbbb2_b2657cc3=yes CC_OUTPUT_921dbbb2_380987f7=yes CC_OUTPUT_921dbbb2_160933ec=yes CC_OUTPUT_921dbbb2_fb62803b=yes _OBJC_CCVERSION_921dbbb2=FreeBSD clang version 14.0.5 (https://github.com/llvm/llvm-project.git llvmorg-14.0.5-0-gc12386ae247c) Target: x86_64-unknown-freebsd14.0 Thread model: posix InstalledDir: /usr/bin _OBJC_ALTCCVERSION_921dbbb2=none ARCH=amd64 OPSYS=FreeBSD _OSRELEASE=14.0-CURRENT OSREL=14.0 OSVERSION=1400067 PYTHONBASE=/usr/local HAVE_COMPAT_IA32_KERN=YES CONFIGURE_MAX_CMD_LEN=524288 HAVE_PORTS_ENV=1 #### Misc Poudriere #### GID=0 UID=0 ---End make.conf--- --Resource limits-- cpu time (seconds, -t) unlimited file size (512-blocks, -f) unlimited data seg size (kbytes, -d) 33554432 stack size (kbytes, -s) 524288 core file size (512-blocks, -c) unlimited max memory size (kbytes, -m) unlimited locked memory (kbytes, -l) unlimited max user processes (-u) 89999 open files (-n) 1024 virtual mem size (kbytes, -v) unlimited swap limit (kbytes, -w) unlimited socket buffer size (bytes, -b) unlimited pseudo-terminals (-p) unlimited kqueues (-k) unlimited umtx shared locks (-o) unlimited --End resource limits-- =================================================== ===> License APACHE20 accepted by the user =========================================================================== =================================================== ===> lattice-ice40-examples-hx1k-g20180310_1 depends on file: /usr/local/sbin/pkg - not found ===> Installing existing package /packages/All/pkg-1.18.4.pkg [main-amd64-default-job-04] Installing pkg-1.18.4... [main-amd64-default-job-04] Extracting pkg-1.18.4: .......... done ===> lattice-ice40-examples-hx1k-g20180310_1 depends on file: /usr/local/sbin/pkg - found ===> Returning to build of lattice-ice40-examples-hx1k-g20180310_1 =========================================================================== =================================================== =========================================================================== =================================================== ===> License APACHE20 accepted by the user ===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310_1 for building =========================================================================== =================================================== ===> License APACHE20 accepted by the user ===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310_1 for building => SHA256 Checksum OK for OLIMEX-iCE40HX1K-EVB-g20180310-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz. =========================================================================== =================================================== =========================================================================== =================================================== ===> License APACHE20 accepted by the user ===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310_1 for building ===> Extracting for lattice-ice40-examples-hx1k-g20180310_1 => SHA256 Checksum OK for OLIMEX-iCE40HX1K-EVB-g20180310-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz. =========================================================================== =================================================== =========================================================================== =================================================== ===> Patching for lattice-ice40-examples-hx1k-g20180310_1 =========================================================================== =================================================== ===> lattice-ice40-examples-hx1k-g20180310_1 depends on executable: abc - not found ===> Installing existing package /packages/All/abc-g20200322.pkg [main-amd64-default-job-04] Installing abc-g20200322... [main-amd64-default-job-04] `-- Installing readline-8.1.2... [main-amd64-default-job-04] | `-- Installing indexinfo-0.3.1... [main-amd64-default-job-04] | `-- Extracting indexinfo-0.3.1: .... done [main-amd64-default-job-04] `-- Extracting readline-8.1.2: .......... done [main-amd64-default-job-04] Extracting abc-g20200322: ..... done ===> lattice-ice40-examples-hx1k-g20180310_1 depends on executable: abc - found Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.32.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 2.32.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $not. Using template $paramod$3b7577489eb4433b1d5620cab7f3794743dee5ea\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_and. Using template $paramod$091610cd349a68bd5539cffd7126f0d76e9bca00\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $eq. Using template $paramod$8f780356cb6cdb52f6a744190131b65634639c4e\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $pos. No more expansions possible. 2.33. Executing OPT pass (performing simple optimizations). 2.33.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.33.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 18 cells. 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 46 unused cells and 76 unused wires. 2.33.5. Finished fast OPT passes. 2.34. Executing ICE40_OPT pass (performing simple optimizations). 2.34.1. Running ICE40 specific optimizations. Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$504.slice[0].carry: CO=\cntr [1] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$515.slice[0].carry: CO=\clk_div [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$518.slice[0].carry: CO=\cntr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$521.slice[0].carry: CO=\rst_cnt [0] 2.34.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.34.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 0 unused wires. 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 2.34.7. Running ICE40 specific optimizations. 2.34.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.34.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.34.12. Finished OPT passes. (There is nothing left to do.) 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2.36. Executing TECHMAP pass (map to technology primitives). 2.36.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 2.36.2. Continuing TECHMAP pass. Using template \$_DFF_P_ for cells of type $_DFF_P_. Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_. Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_. No more expansions possible. 2.37. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping top.$auto$alumacc.cc:485:replace_alu$515.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$518.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$521.slice[0].carry ($lut). 2.39. Executing ICE40_OPT pass (performing simple optimizations). 2.39.1. Running ICE40 specific optimizations. 2.39.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.39.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 46 cells. 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 303 unused wires. 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 2.39.7. Running ICE40 specific optimizations. 2.39.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.39.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.39.12. Finished OPT passes. (There is nothing left to do.) 2.40. Executing TECHMAP pass (map to technology primitives). 2.40.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 2.40.2. Continuing TECHMAP pass. No more expansions possible. 2.41. Executing ABC pass (technology mapping using ABC). 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. Extracted 56 gates and 83 wires to a netlist network with 27 inputs and 13 outputs. 2.41.1.1. Executing ABC. ERROR: Can't open ABC output file `/tmp/yosys-abc-5cd3fq/output.blif'. gmake[1]: *** [Makefile:8: example.blif] Error 1 gmake[1]: Leaving directory '/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb' *** Error code 2 Stop. make: stopped in /usr/ports/devel/lattice-ice40-examples-hx1k