Re: HMP scheduling on FreeBSD
- In reply to: Minsoo Choo : "Re: HMP scheduling on FreeBSD"
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Date: Fri, 16 Jan 2026 04:40:31 UTC
On 1/15/26 18:05, Minsoo Choo wrote: > On Thursday, January 15th, 2026 at 8:12 PM, Mark Millard <marklmi@yahoo.com> wrote: > >> >> >> On 1/15/26 12:53, Minsoo Choo wrote: >> >>> On Thursday, January 15th, 2026 at 2:22 PM, Shawn Webb shawn.webb@hardenedbsd.org wrote: >>> >>> Hi Shawn, >>> . . . >>> >>>> One question I have regarding the security posture of heterogeneous >>>> cores is whether constant-time cryptographic/string/math/etc >>>> operations take between cores. Would it be possible for an attacker to >>>> do <something> by virtue of the different types of cores? >>> >>> ISA on different cores for a same chip is identical. For example, an Arm heterogeneous chip should provide same Arm ISA version (e.g. v9.3) rather than different ISA for different cores. The scheduler has no idea on the ISA version of a specific binary. >> >> >> Hmm: https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf >> >> looks to be a counter example, mixing a pair of Cortex-A7 CPUs and a >> Cortex-M4 in the same SOC (my guess for "chip") --with separate >> connections to the AXI and AHB Switch Fabric, sharing External Memory >> and Internal Memory and everything else on that fabric. >> > > From second page: "Arm Cortex-A7 plus Arm Cortex-M4—Heterogeneous Multicore Processing architecture enables the device to run an open operating system like Linux/Android on the Cortex-A7 core and an RTOS like FreeRTOS™ on the Cortex-M4 core." This is not technically big.LITTLE. > >> The statement may be more of an indication of the bounds of the intended >> support? Or of sub-setting which cores are involved for the FreeBSD >> kernel? (Such also may not be as common for 64-bit contexts.) >> >> Even with the same ISA, properties like cache line sizes can differ, >> based on some example of such that I read about some time ago. (Not that >> I could find the reference now.) Again: a point may be to avoid support >> for such that ends up being "too odd" for the complexity to support it >> vs. the normal range of uses for FreeBSD. > > For big.LITTLE, manufacturers cannot make any combinations of arm cores and call it "heterogeneous". big and LITTLE cores have their pair since design stage, such as A7-A15 and A53-A57. Wikipedia's page on ARM big.LITTLE [1] shows three ways to arrange those cores for operating systems. My proposed design is the third (and the latest) one called heterogeneous multi-processing (or HMP) which lets all cores to work concurrently. Ahh, so "same chip" is really more of a big.LITTLE or DynamIQ "unit" of some kind (in arm terms). I'll note that for DynamIQ they started allowing a mix of big and little the same cluster, unlike before. It also allows having a mix of 3 types of cores, instead of just up to 2. QUOTE for: DynamIQ Shared Unit-AE Enabling DynamIQ for Armv8.2 AE CPUs, which enables a mixture of big and LITTLE CPUs to be configured in a single cluster. When Hybrid mode is enabled, DSU-AE supports up to 4 cores (big or LITTLE) in a single cluster, and up to 4MB L3. END QUOTE and: QUOTE for DynamIQ Shared Unit-120AE Enabling DynamIQ for Armv9.2 AE CPUs, with expanded support for up to 14 cores in a single cluster (with no additional restriction on the number of big or LITTLE cores) and up to 32MB L3 END QUOTE I see references to mixes of (picking ones with the A720 involved): A720/A520 Cix CD8180 A720/A520/X4 Qualcomm Snapdragon 8 Gen 3 (SM8650), Samsung Exynos 2400 A720/X4 MediaTek Dimensity 9300 A720/X4/X925 MediaTek Kompanio Ultra 910 (MT8196) While each may be internally uniform, across them there are variations in if the following are supported vs. not: ssbs (8.0), sve (8.2), svebf16 (8.2), svei8mm (8.2), paca (8.4), pacg (8.4), mte (8.5), mte3 (8.5), wfxt (8.7), sve2 (9.0), sveaes (9.0), svebitperm (9.0), svepmull (9.0), svesha3 (9.0), svesm4 (9.0). Even the 2 A720/A520/X4 instances appear to vary for: sve (8.2), svebf16 (8.2), sveei8mm (8.2), wfxt (8.7), sve2 (9.0), sveaes (9.0), svebitperm (9.0), svepmull (9.0), svesha3 (9.0), svesm4 (9.0). (The lists may not be complete.) That gives me a better idea what you were being referred to, at least in an arm context. Thanks. > >> >>> . . . >>> >>>> -- >>>> Shawn Webb >>>> Cofounder / Security Engineer >>>> HardenedBSD >>>> >>>> Signal Username: shawn_webb.74 >>>> Tor-ified Signal: +1 303-901-1600 / shawn_webb_opsec.50 >>>> https://git.hardenedbsd.org/hardenedbsd/pubkeys/-/raw/master/Shawn_Webb/03A4CBEBB82EA5A67D9F3853FF2E67A277F8E1FA.pub.asc >> >> >> >> -- >> === >> Mark Millard >> marklmi at yahoo.com > > [1] https://en.wikipedia.org/wiki/ARM_big.LITTLE#Run-state_migration > > -- === Mark Millard marklmi at yahoo.com