Re: HMP scheduling on FreeBSD

On Thu, 15 Jan 2026 at 18:05, Minsoo Choo <minsoochoo0122@proton.me> wrote:
> > Hmm: https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf
> >
> > looks to be a counter example, mixing a pair of Cortex-A7 CPUs and a
> > Cortex-M4 in the same SOC (my guess for "chip") --with separate
> > connections to the AXI and AHB Switch Fabric, sharing External Memory
> > and Internal Memory and everything else on that fabric.
> >
>
> From second page: "Arm Cortex-A7 plus Arm Cortex-M4—Heterogeneous Multicore Processing architecture enables the device to run an open operating system like Linux/Android on the Cortex-A7 core and an RTOS like FreeRTOS™ on the Cortex-M4 core." This is not technically big.LITTLE.
>

Yeah. Linux has some memory FIFO/doorbell framework now for
communication between chips on a shared AXI bus
to support this style compute. Lots of vendors invented their own IPC
layers for comms between MCUs, DSPs and the
Cortex-A AP cores and then .. well, it's a mess. :-)

> For big.LITTLE, manufacturers cannot make any combinations of arm cores and call it "heterogeneous". big and LITTLE cores have their pair since design stage, such as A7-A15 and A53-A57. Wikipedia's page on ARM big.LITTLE [1] shows three ways to arrange those cores for operating systems. My proposed design is the third (and the latest) one called heterogeneous multi-processing (or HMP) which lets all cores to work concurrently.

There are systems shipping right now with three types of AP cores on
one die. I've had to debug systems in the past with the big/little
cores having
different cache line sizes. It's a mess. Manufacturers will do
whatever they can and patch linux to do whatever they need to. :-)

I've also seen Linux software literally pass the output of "cat
/proc/cpuinfo" to figure out this mess and then will do utterly
baffling things
like decide upon cache management, cpu workload scheduling, etc based
on matching on the contents of said /proc/cpuinfo.

I also believe there are some feature differences between the Intel
power/efficiency cores? I haven't dug too deeply into it.

That's why I'd like to figure out how to describe to userland and the
rest of the kernel all these bits and pieces.
The HMP stuff is a good move towards the scheduler side of stuff but I
really don't want it wrapped up in some
"the kernel will just do it magically" without letting some policy
stuff be configured.


-adrian