Re: HMP scheduling on FreeBSD

On 1/15/26 12:53, Minsoo Choo wrote:
> On Thursday, January 15th, 2026 at 2:22 PM, Shawn Webb <shawn.webb@hardenedbsd.org> wrote:
> 
> Hi Shawn,
> . . .
> 
>>
>> One question I have regarding the security posture of heterogeneous
>> cores is whether constant-time cryptographic/string/math/etc
>> operations take between cores. Would it be possible for an attacker to
>> do <something> by virtue of the different types of cores?
>>
> 
> ISA on different cores for a same chip is identical. For example, an Arm heterogeneous chip should provide same Arm ISA version (e.g. v9.3) rather than different ISA for different cores. The scheduler has no idea on the ISA version of a specific binary.

Hmm: https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf

looks to be a counter example, mixing a pair of Cortex-A7 CPUs and a
Cortex-M4 in the same SOC (my guess for "chip") --with separate
connections to the AXI and AHB Switch Fabric, sharing External Memory
and Internal Memory and everything else on that fabric.

The statement may be more of an indication of the bounds of the intended
support? Or of sub-setting which cores are involved for the FreeBSD
kernel? (Such also may not be as common for 64-bit contexts.)

Even with the same ISA, properties like cache line sizes can differ,
based on some example of such that I read about some time ago. (Not that
I could find the reference now.) Again: a point may be to avoid support
for such that ends up being "too odd" for the complexity to support it
vs. the normal range of uses for FreeBSD.

> . . .
>>
>> --
>> Shawn Webb
>> Cofounder / Security Engineer
>> HardenedBSD
>>
>> Signal Username: shawn_webb.74
>> Tor-ified Signal: +1 303-901-1600 / shawn_webb_opsec.50
>> https://git.hardenedbsd.org/hardenedbsd/pubkeys/-/raw/master/Shawn_Webb/03A4CBEBB82EA5A67D9F3853FF2E67A277F8E1FA.pub.asc
> 
> 


-- 
===
Mark Millard
marklmi at yahoo.com