[Bug 265974] SMR has several missing barriers

https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=265974

--- Comment #13 from commit-hook@FreeBSD.org ---
A commit in branch main references this bug:

URL:
https://cgit.FreeBSD.org/src/commit/?id=8694fd333556addb97acfff1feca6a1e389201ce

commit 8694fd333556addb97acfff1feca6a1e389201ce
Author:     Mark Johnston <markj@FreeBSD.org>
AuthorDate: 2022-09-24 13:18:04 +0000
Commit:     Mark Johnston <markj@FreeBSD.org>
CommitDate: 2022-09-24 13:18:04 +0000

    smr: Fix synchronization in smr_enter()

    smr_enter() must publish its observed read sequence number before
    issuing any subsequent memory operations.  The ordering provided by
    atomic_add_acq_int() is insufficient on some platforms, at least on
    arm64, because it permits reordering of subsequent loads with the store
    to c_seq.

    Thus, use atomic_thread_fence_seq_cst() to issue a store-load barrier
    after publishing the read sequence number.

    On x86, take advantage of the fact that memory operations are not
    reordered with locked instructions to improve code density: we can store
    the observed read sequence and provide a store-load barrier with a
    single operation.

    Based on a patch from Pierre Habouzit <pierre@habouzit.net>.

    PR:             265974
    Reviewed by:    alc
    MFC after:      2 weeks
    Differential Revision:  https://reviews.freebsd.org/D36370

 sys/sys/smr.h | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

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