git: e1f684a16036 - main - arm64: Fix the ICC_SGI1R_EL1 field names
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Date: Wed, 09 Sep 2026 14:23:01 UTC
The branch main has been updated by andrew:
URL: https://cgit.FreeBSD.org/src/commit/?id=e1f684a1603618b63640bcaf35da6e14ef3edb54
commit e1f684a1603618b63640bcaf35da6e14ef3edb54
Author: Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2026-09-07 23:29:49 +0000
Commit: Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2026-09-08 03:05:27 +0000
arm64: Fix the ICC_SGI1R_EL1 field names
Use the field names from the Arm Documentation for the ICC_SGI1R_EL1
register. These will later be generated from a BSD Licensed JSON file
so to reduce the diff for that rename now.
Reviewed by: Kajetan Puchalski <kajetan.puchalski@arm.com>
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D59174
---
sys/arm64/arm64/gic_v3.c | 8 ++++----
sys/arm64/include/armreg.h | 38 +++++++++++++++++++-------------------
sys/arm64/vmm/io/vgic_v3.c | 15 ++++++++-------
3 files changed, 31 insertions(+), 30 deletions(-)
diff --git a/sys/arm64/arm64/gic_v3.c b/sys/arm64/arm64/gic_v3.c
index 3d9f5f2628fb..3f6b0f1f1c0a 100644
--- a/sys/arm64/arm64/gic_v3.c
+++ b/sys/arm64/arm64/gic_v3.c
@@ -1177,13 +1177,13 @@ gic_v3_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
/* Send the IPI to this cpu */
if (CPU_ISSET(i, &cpus)) {
#define ICC_SGI1R_AFFINITY(aff) \
- (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT) | \
- ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT) | \
- ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT))
+ (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_Aff3_SHIFT) | \
+ ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_Aff2_SHIFT) | \
+ ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_Aff1_SHIFT))
/* Set the affinity when the first at this level */
if (val == 0)
val = ICC_SGI1R_AFFINITY(aff) |
- irq << ICC_SGI1R_EL1_SGIID_SHIFT;
+ irq << ICC_SGI1R_INTID_SHIFT;
/* Set the bit to send the IPI to te CPU */
val |= 1 << CPU_AFF0(CPU_AFFINITY(i));
}
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 779485dfa61c..9db452314977 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -830,25 +830,25 @@
#define ICC_SGI1R_EL1_CRn 12
#define ICC_SGI1R_EL1_CRm 11
#define ICC_SGI1R_EL1_op2 5
-#define ICC_SGI1R_EL1_TL_SHIFT 0
-#define ICC_SGI1R_EL1_TL_MASK (0xffffUL << ICC_SGI1R_EL1_TL_SHIFT)
-#define ICC_SGI1R_EL1_TL_VAL(x) ((x) & ICC_SGI1R_EL1_TL_MASK)
-#define ICC_SGI1R_EL1_AFF1_SHIFT 16
-#define ICC_SGI1R_EL1_AFF1_MASK (0xfful << ICC_SGI1R_EL1_AFF1_SHIFT)
-#define ICC_SGI1R_EL1_AFF1_VAL(x) ((x) & ICC_SGI1R_EL1_AFF1_MASK)
-#define ICC_SGI1R_EL1_SGIID_SHIFT 24
-#define ICC_SGI1R_EL1_SGIID_MASK (0xfUL << ICC_SGI1R_EL1_SGIID_SHIFT)
-#define ICC_SGI1R_EL1_SGIID_VAL(x) ((x) & ICC_SGI1R_EL1_SGIID_MASK)
-#define ICC_SGI1R_EL1_AFF2_SHIFT 32
-#define ICC_SGI1R_EL1_AFF2_MASK (0xfful << ICC_SGI1R_EL1_AFF2_SHIFT)
-#define ICC_SGI1R_EL1_AFF2_VAL(x) ((x) & ICC_SGI1R_EL1_AFF2_MASK)
-#define ICC_SGI1R_EL1_RS_SHIFT 44
-#define ICC_SGI1R_EL1_RS_MASK (0xful << ICC_SGI1R_EL1_RS_SHIFT)
-#define ICC_SGI1R_EL1_RS_VAL(x) ((x) & ICC_SGI1R_EL1_RS_MASK)
-#define ICC_SGI1R_EL1_AFF3_SHIFT 48
-#define ICC_SGI1R_EL1_AFF3_MASK (0xfful << ICC_SGI1R_EL1_AFF3_SHIFT)
-#define ICC_SGI1R_EL1_AFF3_VAL(x) ((x) & ICC_SGI1R_EL1_AFF3_MASK)
-#define ICC_SGI1R_EL1_IRM (0x1UL << 40)
+#define ICC_SGI1R_TargetList_SHIFT 0
+#define ICC_SGI1R_TargetList_MASK (0xffffUL << ICC_SGI1R_TargetList_SHIFT)
+#define ICC_SGI1R_TargetList_VAL(x) ((x) & ICC_SGI1R_TargetList_MASK)
+#define ICC_SGI1R_Aff1_SHIFT 16
+#define ICC_SGI1R_Aff1_MASK (0xfful << ICC_SGI1R_Aff1_SHIFT)
+#define ICC_SGI1R_Aff1_VAL(x) ((x) & ICC_SGI1R_Aff1_MASK)
+#define ICC_SGI1R_INTID_SHIFT 24
+#define ICC_SGI1R_INTID_MASK (0xfUL << ICC_SGI1R_INTID_SHIFT)
+#define ICC_SGI1R_INTID_VAL(x) ((x) & ICC_SGI1R_INTID_MASK)
+#define ICC_SGI1R_Aff2_SHIFT 32
+#define ICC_SGI1R_Aff2_MASK (0xfful << ICC_SGI1R_Aff2_SHIFT)
+#define ICC_SGI1R_Aff2_VAL(x) ((x) & ICC_SGI1R_Aff2_MASK)
+#define ICC_SGI1R_IRM (0x1UL << 40)
+#define ICC_SGI1R_RS_SHIFT 44
+#define ICC_SGI1R_RS_MASK (0xful << ICC_SGI1R_RS_SHIFT)
+#define ICC_SGI1R_RS_VAL(x) ((x) & ICC_SGI1R_RS_MASK)
+#define ICC_SGI1R_Aff3_SHIFT 48
+#define ICC_SGI1R_Aff3_MASK (0xfful << ICC_SGI1R_Aff3_SHIFT)
+#define ICC_SGI1R_Aff3_VAL(x) ((x) & ICC_SGI1R_Aff3_MASK)
/* ICC_SRE_EL1 */
#define ICC_SRE_EL1_SRE (1U << 0)
diff --git a/sys/arm64/vmm/io/vgic_v3.c b/sys/arm64/vmm/io/vgic_v3.c
index ff7a2a9a761f..bc5d4403b1a0 100644
--- a/sys/arm64/vmm/io/vgic_v3.c
+++ b/sys/arm64/vmm/io/vgic_v3.c
@@ -1624,19 +1624,20 @@ vgic_v3_icc_sgi1r_write(struct vcpu *vcpu, uint64_t rval, void *arg)
active_cpus = vm_active_cpus(vm);
vcpuid = vcpu_vcpuid(vcpu);
- irqid = ICC_SGI1R_EL1_SGIID_VAL(rval) >> ICC_SGI1R_EL1_SGIID_SHIFT;
- if ((rval & ICC_SGI1R_EL1_IRM) == 0) {
+ irqid = ICC_SGI1R_INTID_VAL(rval) >> ICC_SGI1R_INTID_SHIFT;
+ if ((rval & ICC_SGI1R_IRM) == 0) {
/* Non-zero points at no vcpus */
- if (ICC_SGI1R_EL1_RS_VAL(rval) != 0)
+ if (ICC_SGI1R_RS_VAL(rval) != 0)
return (0);
- aff1 = ICC_SGI1R_EL1_AFF1_VAL(rval) >> ICC_SGI1R_EL1_AFF1_SHIFT;
- aff2 = ICC_SGI1R_EL1_AFF2_VAL(rval) >> ICC_SGI1R_EL1_AFF2_SHIFT;
- aff3 = ICC_SGI1R_EL1_AFF3_VAL(rval) >> ICC_SGI1R_EL1_AFF3_SHIFT;
+ aff1 = ICC_SGI1R_Aff1_VAL(rval) >> ICC_SGI1R_Aff1_SHIFT;
+ aff2 = ICC_SGI1R_Aff2_VAL(rval) >> ICC_SGI1R_Aff2_SHIFT;
+ aff3 = ICC_SGI1R_Aff3_VAL(rval) >> ICC_SGI1R_Aff3_SHIFT;
mpidr = aff3 << MPIDR_AFF3_SHIFT |
aff2 << MPIDR_AFF2_SHIFT | aff1 << MPIDR_AFF1_SHIFT;
- cpus = ICC_SGI1R_EL1_TL_VAL(rval) >> ICC_SGI1R_EL1_TL_SHIFT;
+ cpus = ICC_SGI1R_TargetList_VAL(rval) >>
+ ICC_SGI1R_TargetList_SHIFT;
cpu_off = 0;
while (cpus > 0) {
if (cpus & 1) {