From nobody Mon Oct 19 15:15:27 2026 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4j7fHh1L6vz6whny for ; Mon, 19 Oct 2026 15:15:28 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 4j7fHg65TKz4HQr for ; Mon, 19 Oct 2026 15:15:27 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1792422927; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Qog414VgfW0XW9SEh1+cW9FxKY2sWRvo7WrHekFKo1Y=; b=GtgUoL80HQh9NN7ecnP44lqWR4g+m14ea5JnWHQkBsfrLuQiqYol0VaqiJUfekCBRW+wAu ktY019+sx6ddj6/MWWRn1f643Ks0pg0NpzCPiBHblk+1O1aYygu/hykLsuClKNxgJi5PIH xpYYQmOncjhPO10bs73h7SOdy3EIIDCyntea1qdQY39niTI7rye+fQz/KaHh1HMESWyBe+ O3wB8lZxZdJfc06FKbMke256N5wtesUMWqHgh5BA+Uc+o97y55sk160ZIXodQEaxGELrdR dtGXyZ0xYs74qs15AhESkpW2KYllEhwGsX/gIUYetfpq98vU2NqJSYGUni2vMg== ARC-Seal: i=1; a=rsa-sha256; d=freebsd.org; s=dkim; cv=none; t=1792422927; b=EvjnzGAG6bTT5/1fICfe+TzmME3ncntlg0iimwgxx4EB7+GSQTDmZ8u3BHV8FFKTWAlG6p Px6DbQoz9EK/ojOOJpAMAQ/vMPiybhf1UPLZnfQXwmpGjVDssFD53W6e3Jmlmm9OBI+6k/ 6CG+/KnVc+4Ci4t7ZzZAVDoBohkjP3FhosLHNnk3J1t0OLK9o52VxAw85i2+0I9BV3Dy/+ FJ/+vLuvF5om9nE5WTIvYiAL5b5BS16HUrBK3wdZGLIABl1Y7fWL24pPO9J4HTf5NDVPD1 81Tar31B5ZUgbdfwsHX0sVv5tnrWzIJXfgrFoB/JdLSdM2fwvkGBq3ZQWiY9FQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1792422927; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Qog414VgfW0XW9SEh1+cW9FxKY2sWRvo7WrHekFKo1Y=; b=FFxYW37G/H0ss5oE/W3j1cNgVRZES3ehwA8Rt9GnuUFKYkmHtsVBp7MyCtmyQ94OiuGRSK bWNxfFbK69fzqKOTfLyk1H9tiK2sM+fkxr8T9FOFHTPvY8/KoQXB/JUZRF/+nBoaZ4f3+T 1JPWOOG1di1Ru6Bshpra6bSHsD2k/ZB+27TcQjiqcieqqZaU7RyZV8FsyXpOM0ZWpL4dSL pLpccJBWZm4Gl8DCJhIDoPavjnk0yXxN0P7hVufCCaYW8qt2FaXxCPbmvX4/Gc7aoSUFFn U9ulzc3L6ceTx3WGPMJQYJ4Arr7yAuFkfpkea35ofdtGOQNTlZAVzwOSSXZuZw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4j7fHg4MgBzQ8Y for ; Mon, 19 Oct 2026 15:15:27 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 42edb by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Mon, 19 Oct 2026 15:15:27 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Abdelkader Boudih Subject: git: 6690cbdc649e - main - intel: add a shared header for the LPSS private registers List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org List-Id: Commit messages for the main branch of the src repository List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: seuros X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 6690cbdc649e7d0b23d96e1490b72068fc791a95 Auto-Submitted: auto-generated Date: Mon, 19 Oct 2026 15:15:27 +0000 Message-Id: <6ad6340f.42edb.3de9b0e4@gitrepo.freebsd.org> The branch main has been updated by seuros: URL: https://cgit.FreeBSD.org/src/commit/?id=6690cbdc649e7d0b23d96e1490b72068fc791a95 commit 6690cbdc649e7d0b23d96e1490b72068fc791a95 Author: Abdelkader Boudih AuthorDate: 2026-10-19 15:15:09 +0000 Commit: Abdelkader Boudih CommitDate: 2026-10-19 15:15:09 +0000 intel: add a shared header for the LPSS private registers The Intel Low Power Subsystem wraps its I2C, SPI and UART functions in a block of private registers that control the functional clock and the function and DMA resets. Refactored to use a single header Reviewed by: imp, adrian Differential Revision: https://reviews.freebsd.org/D60859 --- sys/dev/intel/lpss.h | 35 +++++++++++++++++++++++++++++++++++ sys/dev/intel/spi.c | 15 +++++++-------- sys/dev/uart/uart_bus_pci.c | 21 ++++++++------------- 3 files changed, 50 insertions(+), 21 deletions(-) diff --git a/sys/dev/intel/lpss.h b/sys/dev/intel/lpss.h new file mode 100644 index 000000000000..688195048cb6 --- /dev/null +++ b/sys/dev/intel/lpss.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2026 Abdelkader Boudih + * + * SPDX-License-Identifier: BSD-2-Clause + */ + +#ifndef _DEV_INTEL_LPSS_H_ +#define _DEV_INTEL_LPSS_H_ + +/* + * Intel LPSS private registers, shared by the I2C, SPI and UART functions. + * Offsets are relative to the private block, which sits at one of these + * bases in the function's first memory BAR. + */ +#define LPSS_PRIV_LPT 0x800 /* Lynx Point, Atom SoCs */ +#define LPSS_PRIV_BYT 0x400 /* Bay Trail, Braswell */ +#define LPSS_PRIV_SPT 0x200 /* Sunrise Point and later */ + +/* CLK - functional clock gate and M/N divider; rate is reference * M / N. */ +#define LPSS_PRIV_CLK 0x00 +#define LPSS_PRIV_CLK_EN (1U << 0) +#define LPSS_PRIV_CLK_M_SHIFT 1 +#define LPSS_PRIV_CLK_N_SHIFT 16 +#define LPSS_PRIV_CLK_MN_MASK 0x7fff +#define LPSS_PRIV_CLK_UPDATE (1U << 31) /* latch M and N */ +#define LPSS_PRIV_CLK_MN(m, n) \ + ((((n) & LPSS_PRIV_CLK_MN_MASK) << LPSS_PRIV_CLK_N_SHIFT) | \ + (((m) & LPSS_PRIV_CLK_MN_MASK) << LPSS_PRIV_CLK_M_SHIFT)) + +/* RESETS - function and DMA resets; polarity is inverted from SPT onwards. */ +#define LPSS_PRIV_RESETS 0x04 +#define LPSS_PRIV_RESETS_FUNC 0x3 +#define LPSS_PRIV_RESETS_IDMA (1U << 2) + +#endif /* _DEV_INTEL_LPSS_H_ */ diff --git a/sys/dev/intel/spi.c b/sys/dev/intel/spi.c index 9a0d4305227d..fca74b2f96cc 100644 --- a/sys/dev/intel/spi.c +++ b/sys/dev/intel/spi.c @@ -42,6 +42,7 @@ #include #include +#include #include /** @@ -123,9 +124,7 @@ #define SPI_CS_CTRL_HW_MODE (1 << 0) #define SPI_CS_CTRL_CS_HIGH (1 << 1) -#define INTELSPI_RESETS 0x204 -#define INTELSPI_RESET_HOST (1 << 0) | (1 << 1) -#define INTELSPI_RESET_DMA (1 << 2) +#define INTELSPI_RESETS (LPSS_PRIV_SPT + LPSS_PRIV_RESETS) /* Same order as intelspi_vers */ static const struct intelspi_info { @@ -133,19 +132,19 @@ static const struct intelspi_info { uint32_t reg_cs_ctrl; } intelspi_infos[] = { [SPI_BAYTRAIL] = { - .reg_lpss_base = 0x400, + .reg_lpss_base = LPSS_PRIV_BYT, .reg_cs_ctrl = 0x18, }, [SPI_BRASWELL] = { - .reg_lpss_base = 0x400, + .reg_lpss_base = LPSS_PRIV_BYT, .reg_cs_ctrl = 0x18, }, [SPI_LYNXPOINT] = { - .reg_lpss_base = 0x800, + .reg_lpss_base = LPSS_PRIV_LPT, .reg_cs_ctrl = 0x18, }, [SPI_SUNRISEPOINT] = { - .reg_lpss_base = 0x200, + .reg_lpss_base = LPSS_PRIV_SPT, .reg_cs_ctrl = 0x24, }, }; @@ -509,7 +508,7 @@ intelspi_attach(device_t dev) /* Release LPSS reset */ if (sc->sc_vers == SPI_SUNRISEPOINT) INTELSPI_WRITE(sc, INTELSPI_RESETS, - (INTELSPI_RESET_HOST | INTELSPI_RESET_DMA)); + LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA); sc->sc_irq_res = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, &sc->sc_irq_rid, RF_ACTIVE | RF_SHAREABLE); diff --git a/sys/dev/uart/uart_bus_pci.c b/sys/dev/uart/uart_bus_pci.c index 39d3b1323bed..bb7e58a19f99 100644 --- a/sys/dev/uart/uart_bus_pci.c +++ b/sys/dev/uart/uart_bus_pci.c @@ -35,6 +35,7 @@ #include #include +#include #include #include @@ -85,12 +86,8 @@ struct pci_unique_id { #define PCI_INTEL_LPSS 0x20000000 #define PCI_RID_MASK 0x0000ffff -/* Intel LPSS private registers, relative to BAR0. */ -#define LPSS_CLK 0x200 -#define LPSS_CLK_EN (1U << 0) -#define LPSS_CLK_UPDATE (1U << 31) -#define LPSS_RESETS 0x204 -#define LPSS_RESETS_FUNC 0x3 +#define LPSS_CLK (LPSS_PRIV_SPT + LPSS_PRIV_CLK) +#define LPSS_RESETS (LPSS_PRIV_SPT + LPSS_PRIV_RESETS) static const struct pci_id pci_ns8250_ids[] = { { 0x1028, 0x0008, 0xffff, 0, "Dell Remote Access Card III", 0x14, @@ -258,19 +255,17 @@ uart_pci_lpss_setup(struct resource *res) return (ENXIO); resets = bus_read_4(res, LPSS_RESETS); - bus_write_4(res, LPSS_RESETS, resets | LPSS_RESETS_FUNC); + bus_write_4(res, LPSS_RESETS, resets | LPSS_PRIV_RESETS_FUNC); bus_barrier(res, LPSS_RESETS, sizeof(uint32_t), BUS_SPACE_BARRIER_WRITE); - /* - * Divide the 100 MHz reference clock down to 44.2368 MHz. Bits - * 15:1 hold M and bits 30:16 hold N, giving a rate of ref * M / N. - */ - clk = (15625U << 16) | (6912U << 1); + /* Divide the 100 MHz reference clock down to 44.2368 MHz. */ + clk = LPSS_PRIV_CLK_MN(6912, 15625); bus_write_4(res, LPSS_CLK, clk); bus_barrier(res, LPSS_CLK, sizeof(uint32_t), BUS_SPACE_BARRIER_WRITE); - bus_write_4(res, LPSS_CLK, clk | LPSS_CLK_EN | LPSS_CLK_UPDATE); + bus_write_4(res, LPSS_CLK, + clk | LPSS_PRIV_CLK_EN | LPSS_PRIV_CLK_UPDATE); (void)bus_read_4(res, LPSS_CLK); return (0);