From nobody Tue Oct 13 15:44:58 2026 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4j3zDV4NlSz6vY2T for ; Tue, 13 Oct 2026 15:44:58 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4j3zDV2V6Wz4Pnf for ; Tue, 13 Oct 2026 15:44:58 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791906298; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=xwL81p8hvEJlxcL+lPRGsdyGkADnWe01vLD/II456WY=; b=mz7kr9pfGy6O8N+mB4EGD/BISeUg8jXbZYAiHvFuxAEJUSeMLrAufYWAJ8Bqx5TaRPlASU GuzaljAdw1IkuI2J+AnQnKbx3O1HyVF7u8hNXQoaSnvatVbks00gSy1lksaHyq0udNlUzj FpO+K4nWAQxWY+SCFLMT+Y9njw8ND65xpCQCYyFZnQ7Ajj2rkOqrcHOV2A2HhKOgBSsETG 3cvw+93KMRgD4sYea1nvdpdKGpS5kecDvJY+0yP7XVnSqAQOwjhZGIuCCFRkOffXq+6Mys L5akQQHOdJL4ediyydu1Io70Qm2VOhfeH5zW5lwth5stzZjnEPlgIoGgec1vew== ARC-Seal: i=1; a=rsa-sha256; d=freebsd.org; s=dkim; cv=none; t=1791906298; b=BB8n7ZyiWsCmQ9WbOsS1h7hj2P1JlNoMsRWwTQ77Xt7Co0ip9yxiGN3AIf5mmgm7NCvqMB t4fv8xxjsi/cwE7BXlcvuQWp0uXLMD8xfOvE9Mzm41ka1jMvWx5R4G7SVH7kXgHoa811q5 tMyAgKLskw23NHk128jgd3ZtqrmHWKX66Uu5Ujd81vL+xSb62goQG4QVHPHYiGxvC16VCG IpjG8ch7qNAb4G8Yi8CJTWMwlx0m+RWIQ9Lwn/KS1PkkSPllPjAdRl2DiZTlQ6okWKSoqv OKOsIPnxQs91AfIHQTgdqqyqDWZKxDxA83SUayFACwCtUtRKhkFLYXTAKE6Buw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791906298; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=xwL81p8hvEJlxcL+lPRGsdyGkADnWe01vLD/II456WY=; b=iS8jVpQCZ46V2U/z/sjgy7Jsj+iKu0iOFCPs/FEX6Z7MbW6t5xkKUHYmcAzmCD4dEzSCHk Xg8VHzlL4iEAfIQmp0B7ZGvAHZ2pMEIEQ5ldUdP8HSZvPj0swVwX69DARq/leoIQO1EY4A nC9/qF15YAYEVutKjl/7tK38ceK+/UHIm79evdChQvyFrNNfZezT0YZZdRBbnVkeJ3bX7r Qw0QTHgQbaNvNbQVdwX3osNccpSguKajiKF3GyXE9V+fMOdNvOK/rhH10sOoGmx0Hqgza+ UNEXImT90DRhHeWDJQg5I2s7jVqXzbru0KDedrECi86mb85EexFyp+VJ9CTZTg== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4j3zDV0r85zKXj for ; Tue, 13 Oct 2026 15:44:58 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 21495 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Tue, 13 Oct 2026 15:44:58 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: ac64294143ff - main - arm64: Relax memory barriers around DMA operations List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org List-Id: Commit messages for the main branch of the src repository List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: ac64294143ffea63c7dedf9a1859f88342bd998a Auto-Submitted: auto-generated Date: Tue, 13 Oct 2026 15:44:58 +0000 Message-Id: <6ace51fa.21495.6d2cbee2@gitrepo.freebsd.org> The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=ac64294143ffea63c7dedf9a1859f88342bd998a commit ac64294143ffea63c7dedf9a1859f88342bd998a Author: Andrew Turner AuthorDate: 2026-10-13 15:36:16 +0000 Commit: Andrew Turner CommitDate: 2026-10-13 15:44:34 +0000 arm64: Relax memory barriers around DMA operations Before and after DMA operations we need memory barriers to ensure stores on the CPU are observed by the device, and stores by the device are observed by the CPU. Previously we used a "dsb sy" instruction, however this is too strong and can lead to slower performance. Drew Gallatin found and tested the issue with cache-coherent devices, reducing the barriers to dmb instructions in the outer-shareable domain. After discussing the issue with the Arm Linux DMA maintainer I concluded it was safe for non-coherent devices as the only dsb instructions we need are after cache operations and these already exist. Replace the dsb before DMA with a "dmb oshst" when cache-coherent, or the existing dsb after invalidating the cache when not coherent. This ensures earlier stores have completed before we signal the device. Replace the dsb after DMA with "dmb oshld" in both cases. This ensures later loads or stores are ordered after earlier device register loads. Co-Authored-By: Andrew Gallatin Sponsored by: Arm Ltd Sponsored by: Netflix Differential Revision: https://reviews.freebsd.org/D60407 --- sys/arm64/arm64/busdma_bounce.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/sys/arm64/arm64/busdma_bounce.c b/sys/arm64/arm64/busdma_bounce.c index 49587b5f4b39..d71d114ca60a 100644 --- a/sys/arm64/arm64/busdma_bounce.c +++ b/sys/arm64/arm64/busdma_bounce.c @@ -1101,7 +1101,7 @@ bounce_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, /* * Wait for any DMA operations to complete before the bcopy. */ - dsb(sy); + dmb(oshld); } if (map == NULL) goto out; @@ -1176,11 +1176,17 @@ bounce_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, } out: - if ((op & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) != 0) { + /* + * If the device is cache-coherent then the cache operation will + * have performed a dsb instruction so we don't need another + * barrier here. + */ + if ((map == NULL || (map->flags & DMAMAP_COHERENT) != 0) && + (op & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) != 0) { /* * Wait for the bcopy to complete before any DMA operations. */ - dsb(sy); + dmb(oshst); } if (map != NULL)