From nobody Tue Oct 13 15:44:57 2026 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4j3zDT1thCz6vYCk for ; Tue, 13 Oct 2026 15:44:57 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4j3zDT1Hs1z4Pvl for ; Tue, 13 Oct 2026 15:44:57 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791906297; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=or+IZRD1CGus7zbSQdlhkp9GEZ/Jkob095Wzck7zBK0=; b=Kj6ZvRXhufI3QsBQzgI1RBgbpHAmy9ZyB37w5l8Yv3WIYhIM9p9PtLaAS+wC8iMrclDWhE RkN5bMmHbpGPvigy81UyG46bQeDWvLXEStmw4Kn33ei1Jos5w0xnLh8DlKHRxeHQiHVVfG oPPh7xRDCglEHYNiHp1tdxSyeyDHkS8z7ur3RqJnkeK4Us34IFAOGQGkEQRTE76aIz3fNd y6fvZuEEi5/cYfp5aKXp7kxS+WpZPQiq4abtrPkC3E5UyMkF+zE3MAoEv+iME6/NSPuHV2 NMK2mOyFFfYIz6g1/++VUdB7HDPBh95v6VMWZ242zRIGETjiv+KiSV74ex8xHQ== ARC-Seal: i=1; a=rsa-sha256; d=freebsd.org; s=dkim; cv=none; t=1791906297; b=IemqYYIi65OM0H2kDMjWUdCRa66jP2lG/M9S9ywA1mKgp5p3spHL/Lbgqdq7saOvKO8TXT cg/npyUELqvhY2MIXNeKSsKoJsEMUpJMYDFtbymeFqRt0e7O+Y1yobBCHmOpH6BEe/lshk gcf3LV61DEC+ULIjYpoKziHPqlk8ilhtJIQWeKw9dKfsWTasR8guVi4nSvQy7vrlxGRNPq TBh4mxaygNuyLZ31ufs/pChviD7SXndgEnqtZDFq/duSqZhifcUlIvTFZgSvKX2g8l5X5K 4aGULJTQCOPL6EqfYbfs+nfkvd4f7YCBfUei+ZGaL7+tFReIRhsdmrjNtmVnJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791906297; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=or+IZRD1CGus7zbSQdlhkp9GEZ/Jkob095Wzck7zBK0=; b=Q0Y89J+aawU13ewZGVsxlQBkaI+9aASwV5NQQM2SbxAtEVohhA9Fgl9O83LYI54FQ7VSj6 R3nUidtODJrYdVuUH2mSD5CcwZStMzJkI2oEVCFnUg1LHhWldPSE//t+hkTpvmP1hO9Y5F HuVKHEF/j3Ga3p3Yu1u+q50UPZx4EbXGMyDG7TL2++31hIK4non86yxiUzs6INAxDYuJ72 t0SyFOPVkg7qIcv3cyX6LxcNemP0IcANYVvW45vzeObzpxfLGhzFv6QR3rExlhJA/XBt18 9f9JN7CKl6tTAagNGtHwyNeQCSNeGke2gvx0NyXnf4gmzkSfiOrwSXW9/ACPhw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4j3zDT0439zLG3 for ; Tue, 13 Oct 2026 15:44:57 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 21873 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Tue, 13 Oct 2026 15:44:57 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Cc: Kajetan Puchalski From: Andrew Turner Subject: git: 167d3567c4b9 - main - arm64/vmm: Treat Rt=31 as xzr in reg & instr emul List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org List-Id: Commit messages for the main branch of the src repository List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 167d3567c4b93650c8bcca86ff294226e6e1a9ce Auto-Submitted: auto-generated Date: Tue, 13 Oct 2026 15:44:57 +0000 Message-Id: <6ace51f9.21873.27ce126@gitrepo.freebsd.org> The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=167d3567c4b93650c8bcca86ff294226e6e1a9ce commit 167d3567c4b93650c8bcca86ff294226e6e1a9ce Author: Kajetan Puchalski AuthorDate: 2026-09-29 17:02:19 +0000 Commit: Andrew Turner CommitDate: 2026-10-13 15:44:34 +0000 arm64/vmm: Treat Rt=31 as xzr in reg & instr emul For certain instructions like msr, mrs, ldr & str, Rt=31 means the operand is the Zero register (XZR) as opposed to the SP, even though the two share the encoding of 31 on AArch64. This is currently ignored in register and instruction emulation, so emulated guest operations like "msr , xzr" will set the value of to the current value of the SP instead of to 0. Skip set and get operations when Rt=31 to correct the behaviour. Signed-off-by: Kajetan Puchalski Reviewed by: andrew Sponsored by: Arm Ltd Pull Request: https://github.com/freebsd/freebsd-src/pull/2454 --- sys/arm64/vmm/vmm_instruction_emul.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) diff --git a/sys/arm64/vmm/vmm_instruction_emul.c b/sys/arm64/vmm/vmm_instruction_emul.c index 3d3326d6eda5..484539e9cc52 100644 --- a/sys/arm64/vmm/vmm_instruction_emul.c +++ b/sys/arm64/vmm/vmm_instruction_emul.c @@ -63,11 +63,16 @@ vmm_emulate_instruction(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, error = memread(vcpu, gpa, &val, vie->access_size, memarg); if (error) goto out; - error = vm_set_register(vcpu, vie->reg, val); + /* Make sure we treat Rt=31 as xzr and not SP */ + if (vie->reg != 31) + error = vm_set_register(vcpu, vie->reg, val); } else { - error = vm_get_register(vcpu, vie->reg, &val); - if (error) - goto out; + val = 0; + if (vie->reg != 31) { + error = vm_get_register(vcpu, vie->reg, &val); + if (error) + goto out; + } /* Mask any unneeded bits from the register */ if (vie->access_size < 8) val &= (1ul << (vie->access_size * 8)) - 1; @@ -89,11 +94,23 @@ vmm_emulate_register(struct vcpu *vcpu, struct vre *vre, reg_read_t regread, error = regread(vcpu, &val, regarg); if (error) goto out; - error = vm_set_register(vcpu, vre->reg, val); + /* + * vre->reg here comes from msr/mrs Rt, where 31 means "xzr" as + * opposed to "SP". Reading into xzr must not set the register. + */ + if (vre->reg != 31) + error = vm_set_register(vcpu, vre->reg, val); } else { - error = vm_get_register(vcpu, vre->reg, &val); - if (error) - goto out; + val = 0; + /* + * Writing xzr into a register must write 0, instead of the + * value of SP. + */ + if (vre->reg != 31) { + error = vm_get_register(vcpu, vre->reg, &val); + if (error) + goto out; + } error = regwrite(vcpu, val, regarg); }