git: 3864fe931732 - main - arm64: Add a header for system instructions

The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=3864fe9317325e6abddf7b7126873918533231f8

commit 3864fe9317325e6abddf7b7126873918533231f8
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2026-10-09 11:54:56 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2026-10-09 11:54:56 +0000

    arm64: Add a header for system instructions
    
    Like armreg.h for system registers add a header to hold macros for
    system instructions.
    
    Reviewed by:    jhb
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D59147
---
 sys/arm64/include/_armreg.h |  3 ++-
 sys/arm64/include/sysinsn.h | 40 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/sys/arm64/include/_armreg.h b/sys/arm64/include/_armreg.h
index e00a2b2033af..1f31674318d3 100644
--- a/sys/arm64/include/_armreg.h
+++ b/sys/arm64/include/_armreg.h
@@ -29,7 +29,8 @@
 
 #if !defined(_MACHINE_ARMREG_H_) && \
     !defined(_MACHINE_CPU_H_) && \
-    !defined(_MACHINE_HYPERVISOR_H_)
+    !defined(_MACHINE_HYPERVISOR_H_) && \
+    !defined(_MACHINE_SYSINSN_H_)
 #error Do not include this file directly
 #endif
 
diff --git a/sys/arm64/include/sysinsn.h b/sys/arm64/include/sysinsn.h
new file mode 100644
index 000000000000..f18c62081b7a
--- /dev/null
+++ b/sys/arm64/include/sysinsn.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2026 Arm Ltd
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#ifndef _MACHINE_SYSINSN_H_
+#define	_MACHINE_SYSINSN_H_
+
+#include <machine/_armreg.h>
+
+#define	TLBI_RVAAE1IS_op0	1
+#define	TLBI_RVAAE1IS_op1	0
+#define	TLBI_RVAAE1IS_CRn	8
+#define	TLBI_RVAAE1IS_CRm	2
+#define	TLBI_RVAAE1IS_op2	3
+#define	tlbi_rvaae1is(x)	SYS_ARG(TLBI_RVAAE1IS, x)
+
+#define	TLBI_RVAALE1IS_op0	1
+#define	TLBI_RVAALE1IS_op1	0
+#define	TLBI_RVAALE1IS_CRn	8
+#define	TLBI_RVAALE1IS_CRm	2
+#define	TLBI_RVAALE1IS_op2	7
+#define	tlbi_rvaale1is(x)	SYS_ARG(TLBI_RVAALE1IS, x)
+
+#define	TLBI_RVAE1IS_op0	1
+#define	TLBI_RVAE1IS_op1	0
+#define	TLBI_RVAE1IS_CRn	8
+#define	TLBI_RVAE1IS_CRm	2
+#define	TLBI_RVAE1IS_op2	1
+#define	tlbi_rvae1is(x)		SYS_ARG(TLBI_RVAE1IS, x)
+
+#define	TLBI_RVALE1IS_op0	1
+#define	TLBI_RVALE1IS_op1	0
+#define	TLBI_RVALE1IS_CRn	8
+#define	TLBI_RVALE1IS_CRm	2
+#define	TLBI_RVALE1IS_op2	5
+#define	tlbi_rvale1is(x)	SYS_ARG(TLBI_RVALE1IS, x)
+
+#endif