From nobody Fri Oct 09 12:07:56 2026 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4j1Qbx1T8Zz6vM5P for ; Fri, 09 Oct 2026 12:07:57 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4j1Qbw5shTz3C4q for ; Fri, 09 Oct 2026 12:07:56 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791547676; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=W5Nk8DQbBzfqws40gI1PJDXcZjVHsOhgCoDhgL94MeM=; b=Vo8oXFr0bk6sY5iGT4QaQA+W2ZkHEkeT2vjweYpGeSU1WhTKMe7ltaZjZRD3t7p79K7vao OPJjR7iQVfTNVvx2CnX6iE57GfjXO46F4nM+twvLcOHfq9VJAiOjM+HHk6si0LkwFTDh7T TCuFWFlgrjdpSp7hYluH4ycIwJPZSBMnAY37IBSnYITsR8krWndwEGlxkayOyh6w2MibvH CC4kkTGKByTXh4lSac6XG/tswyLJAFqcnXrgxezVb7Klffrj9Q0sC79tR/lj13iE05kxtk b0THSbuziobgmAlBZEZ4Al7HHajfkp+4sHuddp60LA+OXxc75ziVEgU3EXVNLg== ARC-Seal: i=1; a=rsa-sha256; d=freebsd.org; s=dkim; cv=none; t=1791547676; b=klUJWSIe7abkizqvXyuHraamDgOH2/90MI+IkWTMoxt7E2vki7t5oOvnquaAQ04wU7nwyl jfPd804GiPvyq9YYiW+jHFfqtf5z7jQFFoGimdsqMjCNV31q+QxQ5SSlqnksN7j0S12eUt H1V+0IA6S7Pc81Zeqa3Eu1zuoydQl972oA6dUtxAEnh4o/Hpvbobvq+0wcxvz3nSJsx9I3 kosnZn4VvLa5sRlutr5TxFznqqEcUJGeSaDT6F9y5j1g54VP7X6yaMcvm/Kxl2Lp8xdADT 3NMyW2jwwTrx9tMUcuZ8fAL11LAn9wNhDmy4tzWD2clyWMkpvdK6c27JzosxSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791547676; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=W5Nk8DQbBzfqws40gI1PJDXcZjVHsOhgCoDhgL94MeM=; b=yw31WqEmeT5hEQRb4AtxxHkV1UVxPMAAoIWTxPNbaITRm2X2kr374Uc8ENEBdJhOaEbMsd K9TUQI5D3aau5h2tp2uoO52rGO389Aa24KjkHmXmqYGiF/JJIJYv6XIm0aWUr0oBiOr/Sq ZJxafXsQfdTE+U4GRcehwimRurcSpvGKr4fPMBcuI3Qa6TgIn9FGwqWn7n921Ft49UBHsX H6kDRzinL0Z0tNtoDNVE+eXpJq5Xtm7SaxOC28ySMwEYT8g6EA+r9RS+An7AHSefMzy8iU Yo/XR3nE1dv5npc586sgD8tfDOlbHWNmXJN8pO0SBtKCk5rpVD7uAu2D5xjOvA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4j1Qbw4xZNz1PQX for ; Fri, 09 Oct 2026 12:07:56 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 1d0d0 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Fri, 09 Oct 2026 12:07:56 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: 6bf6fe1d70e7 - main - arm64: Fix the MPIDR_EL1 field names List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 6bf6fe1d70e780786a07e759d75eeb256f247fcd Auto-Submitted: auto-generated Date: Fri, 09 Oct 2026 12:07:56 +0000 Message-Id: <6ac8d91c.1d0d0.779c1ad0@gitrepo.freebsd.org> The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=6bf6fe1d70e780786a07e759d75eeb256f247fcd commit 6bf6fe1d70e780786a07e759d75eeb256f247fcd Author: Andrew Turner AuthorDate: 2026-10-09 11:55:14 +0000 Commit: Andrew Turner CommitDate: 2026-10-09 11:55:14 +0000 arm64: Fix the MPIDR_EL1 field names Use the field names from the Arm Documentation for the MPIDR_EL1 register. These will later be generated from a BSD Licensed JSON file so to reduce the diff for that rename now. Reviewed by: kajetan.puchalski_arm.com Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D59176 --- sys/arm64/include/armreg.h | 24 ++++++++++++------------ sys/arm64/vmm/io/vgic_v3.c | 6 +++--- sys/arm64/vmm/vmm_reset.c | 8 ++++---- 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index cf4645ccf899..ecbc33908851 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -2141,22 +2141,22 @@ #define MPIDR_EL1_CRn 0 #define MPIDR_EL1_CRm 0 #define MPIDR_EL1_op2 5 -#define MPIDR_AFF0_SHIFT 0 -#define MPIDR_AFF0_MASK (UL(0xff) << MPIDR_AFF0_SHIFT) -#define MPIDR_AFF0_VAL(x) ((x) & MPIDR_AFF0_MASK) -#define MPIDR_AFF1_SHIFT 8 -#define MPIDR_AFF1_MASK (UL(0xff) << MPIDR_AFF1_SHIFT) -#define MPIDR_AFF1_VAL(x) ((x) & MPIDR_AFF1_MASK) -#define MPIDR_AFF2_SHIFT 16 -#define MPIDR_AFF2_MASK (UL(0xff) << MPIDR_AFF2_SHIFT) -#define MPIDR_AFF2_VAL(x) ((x) & MPIDR_AFF2_MASK) +#define MPIDR_Aff0_SHIFT 0 +#define MPIDR_Aff0_MASK (UL(0xff) << MPIDR_Aff0_SHIFT) +#define MPIDR_Aff0_VAL(x) ((x) & MPIDR_Aff0_MASK) +#define MPIDR_Aff1_SHIFT 8 +#define MPIDR_Aff1_MASK (UL(0xff) << MPIDR_Aff1_SHIFT) +#define MPIDR_Aff1_VAL(x) ((x) & MPIDR_Aff1_MASK) +#define MPIDR_Aff2_SHIFT 16 +#define MPIDR_Aff2_MASK (UL(0xff) << MPIDR_Aff2_SHIFT) +#define MPIDR_Aff2_VAL(x) ((x) & MPIDR_Aff2_MASK) #define MPIDR_MT_SHIFT 24 #define MPIDR_MT_MASK (UL(0x1) << MPIDR_MT_SHIFT) #define MPIDR_U_SHIFT 30 #define MPIDR_U_MASK (UL(0x1) << MPIDR_U_SHIFT) -#define MPIDR_AFF3_SHIFT 32 -#define MPIDR_AFF3_MASK (UL(0xff) << MPIDR_AFF3_SHIFT) -#define MPIDR_AFF3_VAL(x) ((x) & MPIDR_AFF3_MASK) +#define MPIDR_Aff3_SHIFT 32 +#define MPIDR_Aff3_MASK (UL(0xff) << MPIDR_Aff3_SHIFT) +#define MPIDR_Aff3_VAL(x) ((x) & MPIDR_Aff3_MASK) /* MVFR0_EL1 */ #define MVFR0_EL1_ISS ISS_MSR_REG(MVFR0_EL1) diff --git a/sys/arm64/vmm/io/vgic_v3.c b/sys/arm64/vmm/io/vgic_v3.c index d180c2345323..39579ce99dd6 100644 --- a/sys/arm64/vmm/io/vgic_v3.c +++ b/sys/arm64/vmm/io/vgic_v3.c @@ -1633,8 +1633,8 @@ vgic_v3_icc_sgi1r_write(struct vcpu *vcpu, uint64_t rval, void *arg) aff1 = ICC_SGI1R_Aff1_VAL(rval) >> ICC_SGI1R_Aff1_SHIFT; aff2 = ICC_SGI1R_Aff2_VAL(rval) >> ICC_SGI1R_Aff2_SHIFT; aff3 = ICC_SGI1R_Aff3_VAL(rval) >> ICC_SGI1R_Aff3_SHIFT; - mpidr = aff3 << MPIDR_AFF3_SHIFT | - aff2 << MPIDR_AFF2_SHIFT | aff1 << MPIDR_AFF1_SHIFT; + mpidr = aff3 << MPIDR_Aff3_SHIFT | + aff2 << MPIDR_Aff2_SHIFT | aff1 << MPIDR_Aff1_SHIFT; cpus = ICC_SGI1R_TargetList_VAL(rval) >> ICC_SGI1R_TargetList_SHIFT; @@ -1642,7 +1642,7 @@ vgic_v3_icc_sgi1r_write(struct vcpu *vcpu, uint64_t rval, void *arg) while (cpus > 0) { if (cpus & 1) { target_vcpuid = mpidr_to_vcpu(hyp, - mpidr | (cpu_off << MPIDR_AFF0_SHIFT)); + mpidr | (cpu_off << MPIDR_Aff0_SHIFT)); if (target_vcpuid >= 0 && CPU_ISSET(target_vcpuid, &active_cpus)) { INJECT_IRQ(hyp, target_vcpuid, irqid, diff --git a/sys/arm64/vmm/vmm_reset.c b/sys/arm64/vmm/vmm_reset.c index e75a464b0764..4e7b6a7e160f 100644 --- a/sys/arm64/vmm/vmm_reset.c +++ b/sys/arm64/vmm/vmm_reset.c @@ -120,10 +120,10 @@ reset_vm_el2_regs(void *vcpu) * Generate the guest MPIDR value. We only support 16 CPUs at affinity * level 0 to simplify the vgicv3 driver (see writing sgi1r_el1). */ - cpu_aff = (vcpuid & 0xf) << MPIDR_AFF0_SHIFT | - ((vcpuid >> 4) & 0xff) << MPIDR_AFF1_SHIFT | - ((vcpuid >> 12) & 0xff) << MPIDR_AFF2_SHIFT | - ((vcpuid >> 20) & 0xff) << MPIDR_AFF3_SHIFT; + cpu_aff = (vcpuid & 0xf) << MPIDR_Aff0_SHIFT | + ((vcpuid >> 4) & 0xff) << MPIDR_Aff1_SHIFT | + ((vcpuid >> 12) & 0xff) << MPIDR_Aff2_SHIFT | + ((vcpuid >> 20) & 0xff) << MPIDR_Aff3_SHIFT; *hypctx_sys_reg(el2ctx, HOST_VMPIDR_EL2) |= cpu_aff; /* Use the same CPU identification information as the host */