From nobody Fri Oct 09 10:12:32 2026 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4j1N2n1Yvbz6vR41 for ; Fri, 09 Oct 2026 10:12:33 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR2" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4j1N2m6xmSz4XZs for ; Fri, 09 Oct 2026 10:12:32 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791540753; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=fxX/eGVl5eoTGAVjd3ayI8R0QWrGEF+PBjVipL72As8=; b=Ge+C1omAMpw7HRtfTBXuehRWatPGHkctJBYlKrUC36Lsb7d9Ld8iZuGTS9i4+UpJoXG+2S LqQ42uwvvAi1J1YzzfUGtTYVY/hi7YlyjSoZzRQIsOkFZO0ZPDi/KeWytZhTJhEewZUT9L 5+RUaGHbpfEqRX/f7UYUsi4yEIBVXhfle67jD0MajUt4skGX+RTHjFegZfgYc6nLid/4cS 74oIdzNZvYFtPvnXjzIDOFQOplxw9/zcOsn3T0ZZ7C+LbOJOf4KKvUTBeSIwOxJjNn/3b8 Xxt7CqCD2JHHKS0nc+UxMTNbu8uS4TpC4xkAz+1j6L8GyWXNc6mdQHBoEQBM6g== ARC-Seal: i=1; a=rsa-sha256; d=freebsd.org; s=dkim; cv=none; t=1791540753; b=G9PkolukVKlK33lAH6SDadDCuBmvb9PJ7HyFZrTRs+S9ehvfbj8xm15ZB7vCJenRyXqTdR M4NwWA8ZcLBZgiYarjh7jY6sSJPenzTvByAE+oz6R6t89CaVATEgtKNxUOVW6aTkJNt4HM JzY5ls1PWzI0CJojti31SImSYL/ima4hBXKu1Ym9NfJ5+icuZj9N7pgEPRut2jk3MloeXV ujm93BT/nzwS0x6kdfv1s9FkZqT80oWCDliQvbp9n3+WE6n//U6WKIiLKYgOHZocNtNqYb bJq5oSP7Pwl0iGujfrt8WTLUD2pYoJbqhJbY7SBwquByQbqmBuzcHxy5tPQwuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1791540753; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=fxX/eGVl5eoTGAVjd3ayI8R0QWrGEF+PBjVipL72As8=; b=WcaXS/hCjBUxQ5tzIQvmQFhH4juHLIHHzNGQC/SSWvLc1D56vi1OIIAcVhiz7WgK5niDL4 tSKLTJgNz8/xuZQscdmIsNy2CLKpHxYvnQkDqsvORV83HqLGFtqWFzVl1AD4zWGYfaK2AV SfoZxPiCbh0RlH68OQHgpbxtg6BWcTVdFRuicLjD+w0/6wRaBdQ3N5HZaLuCOqHA6X/f8v IiOBSzSAY3T+UIIruPbMAo9mUkvnyWLYpWHNf6II14IL3qb6xzhipFC+8WZuZUpqEfkTDf KPeXb5z6FzCVlEvAXhn18PMiTo6EMMrF+qH08qJOkGdqykBeQiROmGRzrG4jLw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4j1N2m3f7Cz1LZH for ; Fri, 09 Oct 2026 10:12:32 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 42d04 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Fri, 09 Oct 2026 10:12:32 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Cc: Sumit Saxena From: Sumit Saxena Subject: git: 2f3a1ebba812 - main - if_bnxt: add CAGR interrupt coalescing tick-resolution support List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: ssaxena X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 2f3a1ebba81266b5f21640f88d73e03415cf13be Auto-Submitted: auto-generated Date: Fri, 09 Oct 2026 10:12:32 +0000 Message-Id: <6ac8be10.42d04.6082f118@gitrepo.freebsd.org> The branch main has been updated by ssaxena: URL: https://cgit.FreeBSD.org/src/commit/?id=2f3a1ebba81266b5f21640f88d73e03415cf13be commit 2f3a1ebba81266b5f21640f88d73e03415cf13be Author: Sumit Saxena AuthorDate: 2026-07-29 08:36:18 +0000 Commit: Sumit Saxena CommitDate: 2026-10-09 08:24:42 +0000 if_bnxt: add CAGR interrupt coalescing tick-resolution support Add the P7 CAGR (Completion AGgregation Ring) NQ-aggregation timer tick-resolution knob, programmed via a direct GRC-window register write, with a new dev.bnxt..cagr_tick_res read-only tunable. This is independent of the existing per-ring AGGINT_PARAMS coalescing. Reviewed by: gallatin MFC after: 2 weeks Sponsored by: Broadcom Inc. Differential Revision: https://reviews.freebsd.org/D58598 --- sys/dev/bnxt/bnxt_en/bnxt.h | 8 ++++++++ sys/dev/bnxt/bnxt_en/bnxt_sysctl.c | 27 +++++++++++++++++++++++++++ sys/dev/bnxt/bnxt_en/if_bnxt.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/sys/dev/bnxt/bnxt_en/bnxt.h b/sys/dev/bnxt/bnxt_en/bnxt.h index 98f8c1d3f5fa..35f1b9e97a00 100644 --- a/sys/dev/bnxt/bnxt_en/bnxt.h +++ b/sys/dev/bnxt/bnxt_en/bnxt.h @@ -1423,6 +1423,14 @@ struct bnxt_softc { struct bnxt_ptp_cfg *ptp_cfg; bool rx_ts_enabled; + +#define BNXT_CAGR_CQCOAL_OFFSET 0xc00 +#define BNXT_CAGR_NQAGG_MAXTIMER 0x5930000 +#define BNXT_CAGR_TICK_RES_DEFAULT 0x2 +#define BNXT_CAGR_TICK_RES_MIN 0x0 +#define BNXT_CAGR_TICK_RES_MAX 0x4 +#define BNXT_CAGR_TICK_RES_OFFSET 16 + uint32_t cagr_tick_res; }; struct bnxt_filter_info { diff --git a/sys/dev/bnxt/bnxt_en/bnxt_sysctl.c b/sys/dev/bnxt/bnxt_en/bnxt_sysctl.c index 88afc83edd9d..c8a0f1962a13 100644 --- a/sys/dev/bnxt/bnxt_en/bnxt_sysctl.c +++ b/sys/dev/bnxt/bnxt_en/bnxt_sysctl.c @@ -1556,6 +1556,30 @@ bnxt_set_coal_tx_frames_irq(SYSCTL_HANDLER_ARGS) { return rc; } +static int +bnxt_set_cagr_tick_res(SYSCTL_HANDLER_ARGS) { + struct bnxt_softc *softc = arg1; + int rc; + int val; + + if (softc == NULL) + return EBUSY; + + val = softc->cagr_tick_res; + + rc = sysctl_handle_int(oidp, &val, 0, req); + if (rc || !req->newptr) + return rc; + + if (val < BNXT_CAGR_TICK_RES_MIN || + val > BNXT_CAGR_TICK_RES_MAX) + return EINVAL; + + softc->cagr_tick_res = val; + + return rc; +} + static void simulate_reset(struct bnxt_softc *bp, char *fwcli_string) { @@ -1648,6 +1672,9 @@ bnxt_create_config_sysctls_pre(struct bnxt_softc *softc) CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, softc, 0, bnxt_set_coal_tx_frames_irq, "I", "interrupt coalescing Tx Frames IRQ"); + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cagr_tick_res", + CTLTYPE_INT | CTLFLAG_RDTUN | CTLFLAG_MPSAFE, softc, 0, + bnxt_set_cagr_tick_res, "I", "CAGR tick resolution"); SYSCTL_ADD_U32(ctx, children, OID_AUTO, "flags", CTLFLAG_RD, &softc->flags, 0, "flags"); SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fw_cap", CTLFLAG_RD, diff --git a/sys/dev/bnxt/bnxt_en/if_bnxt.c b/sys/dev/bnxt/bnxt_en/if_bnxt.c index 044ab619c399..188311b2d7d4 100644 --- a/sys/dev/bnxt/bnxt_en/if_bnxt.c +++ b/sys/dev/bnxt/bnxt_en/if_bnxt.c @@ -2065,6 +2065,26 @@ static inline void __bnxt_map_fw_health_reg(struct bnxt_softc *bp, u32 reg) BNXT_HWRM_BAR_IDX, reg & BNXT_GRC_BASE_MASK); } +static void +bnxt_set_cqcoal_tick_res(struct bnxt_softc *bp) +{ + u32 val = 0; + u32 cagr_addr = BNXT_GRCPF_REG_WINDOW_BASE_OUT + BNXT_CAGR_CQCOAL_OFFSET; + + if (!BNXT_CHIP_P7(bp)) + return; + + writel_fbsd(bp, BNXT_GRCPF_REG_WINDOW_BASE_OUT, BNXT_HWRM_BAR_IDX, + BNXT_CAGR_NQAGG_MAXTIMER); + val = readl_fbsd(bp, cagr_addr, BNXT_HWRM_BAR_IDX); + + /* Clear out CAGR tick resolution bits(16-19), before writing new value */ + val &= ~(0xf << BNXT_CAGR_TICK_RES_OFFSET); + + writel_fbsd(bp, cagr_addr, BNXT_HWRM_BAR_IDX, + (val | bp->cagr_tick_res << BNXT_CAGR_TICK_RES_OFFSET)); +} + static int bnxt_map_fw_health_regs(struct bnxt_softc *bp) { struct bnxt_fw_health *fw_health = bp->fw_health; @@ -2203,6 +2223,12 @@ static bool bnxt_fw_reset_timeout(struct bnxt_softc *bp) static int bnxt_open(struct bnxt_softc *bp) { int rc = 0; + + /* A function/chip reset drops the CAGR tick-resolution register + * programmed in bnxt_attach_pre(); restore it before we start + * relying on interrupt coalescing again. */ + bnxt_set_cqcoal_tick_res(bp); + if (BNXT_PF(bp)) rc = bnxt_hwrm_nvm_get_dev_info(bp, &bp->nvm_info->mfg_id, &bp->nvm_info->device_id, &bp->nvm_info->sector_size, @@ -2886,6 +2912,10 @@ bnxt_attach_pre(if_ctx_t ctx) HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 | HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 | HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; + + if (BNXT_CHIP_P7(softc)) + softc->cagr_tick_res = BNXT_CAGR_TICK_RES_DEFAULT; + rc = bnxt_create_config_sysctls_pre(softc); if (rc) goto failed; @@ -2930,6 +2960,8 @@ bnxt_attach_pre(if_ctx_t ctx) snprintf(softc->board_partno, sizeof(softc->board_partno), "%s", part_num); } + bnxt_set_cqcoal_tick_res(softc); + return (rc);