git: 3e4cbdebfc9b - main - mlx5: Add support for 800Gbit/s and 400Gbit/s with 2 lanes

The branch main has been updated by kib:

URL: https://cgit.FreeBSD.org/src/commit/?id=3e4cbdebfc9bcb2f2c64acc8ee8f67c3383cd676

commit 3e4cbdebfc9bcb2f2c64acc8ee8f67c3383cd676
Author:     Slava Shwartsman <slavash@nvidia.com>
AuthorDate: 2026-05-13 14:22:48 +0000
Commit:     Konstantin Belousov <kib@FreeBSD.org>
CommitDate: 2026-06-17 18:23:14 +0000

    mlx5: Add support for 800Gbit/s and 400Gbit/s with 2 lanes
    
    Reviewed by:    kib
    Tested by:      Wafa Hamzah <wafah@nvidia.com>
    MFC after:      1 week
    Sponsored by:   NVIDIA Networking
---
 sys/dev/mlx5/mlx5_core/mlx5_port.c  |  4 ++++
 sys/dev/mlx5/mlx5_en/mlx5_en_main.c | 44 +++++++++++++++++++++++++++++++++++++
 sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c | 12 ++++++++++
 sys/dev/mlx5/port.h                 |  3 +++
 4 files changed, 63 insertions(+)

diff --git a/sys/dev/mlx5/mlx5_core/mlx5_port.c b/sys/dev/mlx5/mlx5_core/mlx5_port.c
index af01bfae1b4e..fc192ec6a23b 100644
--- a/sys/dev/mlx5/mlx5_core/mlx5_port.c
+++ b/sys/dev/mlx5/mlx5_core/mlx5_port.c
@@ -1331,6 +1331,10 @@ static const u32 mlx5e_ext_link_speed[/*MLX5E_EXT_LINK_MODES_NUMBER*/] = {
 	[MLX5E_CAUI_4_100GBASE_CR4_KR4]		= 100000,
 	[MLX5E_200GAUI_4_200GBASE_CR4_KR4]	= 200000,
 	[MLX5E_400GAUI_8]			= 400000,
+	[MLX5E_400GAUI_4_400GBASE_CR4_KR4]	= 400000,
+	[MLX5E_400GAUI_2_400GBASE_CR2_KR2]	= 400000,
+	[MLX5E_800GAUI_8_800GBASE_CR8_KR8]	= 800000,
+	[MLX5E_800GAUI_4_800GBASE_CR4_KR4]	= 800000,
 };
 
 static void mlx5e_port_get_speed_arr(struct mlx5_core_dev *mdev,
diff --git a/sys/dev/mlx5/mlx5_en/mlx5_en_main.c b/sys/dev/mlx5/mlx5_en/mlx5_en_main.c
index fb8b79c8f787..35450776e54e 100644
--- a/sys/dev/mlx5/mlx5_en/mlx5_en_main.c
+++ b/sys/dev/mlx5/mlx5_en/mlx5_en_main.c
@@ -352,6 +352,48 @@ static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX
 		.subtype = IFM_400G_LR8,	/* XXX */
 		.baudrate = IF_Gbps(400ULL),
 	},
+
+	/**/
+	[MLX5E_400GAUI_2_400GBASE_CR2_KR2][MLX5E_PORT_UNKNOWN] = {
+		.subtype = IFM_400G_KR2_PAM4,
+		.baudrate = IF_Gbps(400ULL),
+	},
+	[MLX5E_400GAUI_2_400GBASE_CR2_KR2][MLX5E_PORT_DA] = {
+		.subtype = IFM_400G_CR2,
+		.baudrate = IF_Gbps(400ULL),
+	},
+	[MLX5E_400GAUI_2_400GBASE_CR2_KR2][MLX5E_PORT_FIBRE] = {
+		.subtype = IFM_400G_SR2,
+		.baudrate = IF_Gbps(400ULL),
+	},
+
+	/**/
+	[MLX5E_800GAUI_8_800GBASE_CR8_KR8][MLX5E_PORT_UNKNOWN] = {
+		.subtype = IFM_800G_KR8,	/* 800GAUI-8 / KR8a */
+		.baudrate = IF_Gbps(800ULL),
+	},
+	[MLX5E_800GAUI_8_800GBASE_CR8_KR8][MLX5E_PORT_DA] = {
+		.subtype = IFM_800G_CR8,	/* 800GBASE-CR8 */
+		.baudrate = IF_Gbps(800ULL),
+	},
+	[MLX5E_800GAUI_8_800GBASE_CR8_KR8][MLX5E_PORT_FIBRE] = {
+		.subtype = IFM_800G_SR8,
+		.baudrate = IF_Gbps(800ULL),
+	},
+
+	/**/
+	[MLX5E_800GAUI_4_800GBASE_CR4_KR4][MLX5E_PORT_UNKNOWN] = {
+		.subtype = IFM_800G_KR4_PAM4,	/* 800GAUI-4 / KR4 */
+		.baudrate = IF_Gbps(800ULL),
+	},
+	[MLX5E_800GAUI_4_800GBASE_CR4_KR4][MLX5E_PORT_DA] = {
+		.subtype = IFM_800G_CR4,	/* 800GBASE-CR4 */
+		.baudrate = IF_Gbps(800ULL),
+	},
+	[MLX5E_800GAUI_4_800GBASE_CR4_KR4][MLX5E_PORT_FIBRE] = {
+		.subtype = IFM_800G_SR4,
+		.baudrate = IF_Gbps(800ULL),
+	},
 };
 
 static const struct if_snd_tag_sw mlx5e_ul_snd_tag_sw = {
@@ -404,6 +446,8 @@ mlx5e_update_carrier(struct mlx5e_priv *priv)
 	eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 	    eth_proto_oper);
 	connector_type = MLX5_GET(ptys_reg, out, connector_type);
+	if (connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER)
+		connector_type = MLX5E_PORT_UNKNOWN;
 	i = ilog2(eth_proto_oper);
 
 	if (ext) {
diff --git a/sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c b/sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c
index 6ff4e55630d7..cf1e5f4324d8 100644
--- a/sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c
+++ b/sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c
@@ -273,6 +273,18 @@ static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 		*active_width = IB_WIDTH_4X;
 		*active_speed = IB_SPEED_NDR;
 		break;
+	case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2):
+		*active_width = IB_WIDTH_2X;
+		*active_speed = IB_SPEED_XDR;
+		break;
+	case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8):
+		*active_width = IB_WIDTH_8X;
+		*active_speed = IB_SPEED_NDR;
+		break;
+	case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4):
+		*active_width = IB_WIDTH_4X;
+		*active_speed = IB_SPEED_XDR;
+		break;
 	default:
 		*active_width = IB_WIDTH_4X;
 		*active_speed = IB_SPEED_QDR;
diff --git a/sys/dev/mlx5/port.h b/sys/dev/mlx5/port.h
index a35265852ae4..6c1e6e629856 100644
--- a/sys/dev/mlx5/port.h
+++ b/sys/dev/mlx5/port.h
@@ -125,6 +125,9 @@ enum mlx5e_ext_link_speed {
 	MLX5E_200GAUI_2_200GBASE_CR2_KR2	= 13,
 	MLX5E_400GAUI_8				= 15,
 	MLX5E_400GAUI_4_400GBASE_CR4_KR4	= 16,
+	MLX5E_400GAUI_2_400GBASE_CR2_KR2	= 17,
+	MLX5E_800GAUI_8_800GBASE_CR8_KR8	= 19,
+	MLX5E_800GAUI_4_800GBASE_CR4_KR4	= 20,
 	MLX5E_EXT_LINK_SPEEDS_NUMBER		= 32,
 };