git: dda55f83f9b8 - main - cxgbe(4): Update shared code and config files
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Date: Sat, 10 Jan 2026 23:38:24 UTC
The branch main has been updated by np:
URL: https://cgit.FreeBSD.org/src/commit/?id=dda55f83f9b8238ebf2940c9c1e227785db540b2
commit dda55f83f9b8238ebf2940c9c1e227785db540b2
Author: Navdeep Parhar <np@FreeBSD.org>
AuthorDate: 2025-11-20 21:27:48 +0000
Commit: Navdeep Parhar <np@FreeBSD.org>
CommitDate: 2026-01-10 22:44:31 +0000
cxgbe(4): Update shared code and config files
Obtained from: Chelsio Communications
MFC after: 1 week
Sponsored by: Chelsio Communications
---
sys/dev/cxgbe/common/t4_hw.c | 13 +-
sys/dev/cxgbe/common/t4_regs.h | 1056 ++++++++++++++++++++++-------
sys/dev/cxgbe/firmware/t7fw_cfg.txt | 34 +-
sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt | 26 +-
usr.sbin/cxgbetool/reg_defs_t7.c | 722 ++++++++++++++------
5 files changed, 1397 insertions(+), 454 deletions(-)
diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c
index 65292486cbc8..494f83a47135 100644
--- a/sys/dev/cxgbe/common/t4_hw.c
+++ b/sys/dev/cxgbe/common/t4_hw.c
@@ -3282,7 +3282,9 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
0x477d4, 0x477fc,
0x48000, 0x48004,
0x48018, 0x4801c,
- 0x49304, 0x493f0,
+ 0x49304, 0x49320,
+ 0x4932c, 0x4932c,
+ 0x49334, 0x493f0,
0x49400, 0x49410,
0x49460, 0x494f4,
0x50000, 0x50084,
@@ -3305,7 +3307,9 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
0x515f0, 0x515f4,
0x58000, 0x58004,
0x58018, 0x5801c,
- 0x59304, 0x593f0,
+ 0x59304, 0x59320,
+ 0x5932c, 0x5932c,
+ 0x59334, 0x593f0,
0x59400, 0x59410,
0x59460, 0x594f4,
};
@@ -6177,11 +6181,6 @@ static bool mem_intr_handler(struct adapter *adap, int idx, int flags)
ii.cause_reg = MC_T7_REG(A_MC_P_DDRCTL_INT_CAUSE, i);
ii.enable_reg = MC_T7_REG(A_MC_P_DDRCTL_INT_ENABLE, i);
fatal |= t4_handle_intr(adap, &ii, 0, flags);
-
- snprintf(rname, sizeof(rname), "MC%u_ECC_UE_INT_CAUSE", i);
- ii.cause_reg = MC_T7_REG(A_MC_P_ECC_UE_INT_CAUSE, i);
- ii.enable_reg = MC_T7_REG(A_MC_P_ECC_UE_INT_ENABLE, i);
- fatal |= t4_handle_intr(adap, &ii, 0, flags);
}
break;
}
diff --git a/sys/dev/cxgbe/common/t4_regs.h b/sys/dev/cxgbe/common/t4_regs.h
index 51f150443261..09d0d4aa2c08 100644
--- a/sys/dev/cxgbe/common/t4_regs.h
+++ b/sys/dev/cxgbe/common/t4_regs.h
@@ -27,11 +27,11 @@
*/
/* This file is automatically generated --- changes will be lost */
-/* Generation Date : Tue Oct 28 05:23:45 PM IST 2025 */
+/* Generation Date : Thu Dec 11 08:42:50 PM IST 2025 */
/* Directory name: t4_reg.txt, Date: Not specified */
-/* Directory name: t5_reg.txt, Changeset: 6945:54ba4ba7ee8b */
+/* Directory name: t5_reg.txt, Changeset: 6946:9d3868c42009 */
/* Directory name: t6_reg.txt, Changeset: 4277:9c165d0f4899 */
-/* Directory name: t7_sw_reg.txt, Changeset: 5946:0b60ff298e7d */
+/* Directory name: t7_sw_reg.txt, Changeset: 5950:7c934148528c */
#define MYPF_BASE 0x1b000
#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
@@ -6195,15 +6195,15 @@
#define A_PCIE_PF_INT_CFG 0x3140
-#define S_T7_VECNUM 12
-#define M_T7_VECNUM 0x7ffU
-#define V_T7_VECNUM(x) ((x) << S_T7_VECNUM)
-#define G_T7_VECNUM(x) (((x) >> S_T7_VECNUM) & M_T7_VECNUM)
+#define S_T7_PF_INT_VECNUM 12
+#define M_T7_PF_INT_VECNUM 0x7ffU
+#define V_T7_PF_INT_VECNUM(x) ((x) << S_T7_PF_INT_VECNUM)
+#define G_T7_PF_INT_VECNUM(x) (((x) >> S_T7_PF_INT_VECNUM) & M_T7_PF_INT_VECNUM)
-#define S_T7_VECBASE 0
-#define M_T7_VECBASE 0xfffU
-#define V_T7_VECBASE(x) ((x) << S_T7_VECBASE)
-#define G_T7_VECBASE(x) (((x) >> S_T7_VECBASE) & M_T7_VECBASE)
+#define S_T7_PF_INT_VECBASE 0
+#define M_T7_PF_INT_VECBASE 0xfffU
+#define V_T7_PF_INT_VECBASE(x) ((x) << S_T7_PF_INT_VECBASE)
+#define G_T7_PF_INT_VECBASE(x) (((x) >> S_T7_PF_INT_VECBASE) & M_T7_PF_INT_VECBASE)
#define A_PCIE_PF_INT_CFG2 0x3144
#define A_PCIE_VF_INT_CFG 0x3180
@@ -10636,6 +10636,12 @@
#define G_VFID_PCIE(x) (((x) >> S_VFID_PCIE) & M_VFID_PCIE)
#define A_PCIE_VF_INT_INDIR_DATA 0x5c48
+
+#define S_T7_VECBASE 0
+#define M_T7_VECBASE 0xfffU
+#define V_T7_VECBASE(x) ((x) << S_T7_VECBASE)
+#define G_T7_VECBASE(x) (((x) >> S_T7_VECBASE) & M_T7_VECBASE)
+
#define A_PCIE_VF_256_INT_CFG2 0x5c4c
#define A_PCIE_VF_MSI_EN_4 0x5e50
#define A_PCIE_VF_MSI_EN_5 0x5e54
@@ -17723,6 +17729,22 @@
#define V_GPIO20_PE_EN(x) ((x) << S_GPIO20_PE_EN)
#define F_GPIO20_PE_EN V_GPIO20_PE_EN(1U)
+#define S_T7_GPIO19_PE_EN 19
+#define V_T7_GPIO19_PE_EN(x) ((x) << S_T7_GPIO19_PE_EN)
+#define F_T7_GPIO19_PE_EN V_T7_GPIO19_PE_EN(1U)
+
+#define S_T7_GPIO18_PE_EN 18
+#define V_T7_GPIO18_PE_EN(x) ((x) << S_T7_GPIO18_PE_EN)
+#define F_T7_GPIO18_PE_EN V_T7_GPIO18_PE_EN(1U)
+
+#define S_T7_GPIO17_PE_EN 17
+#define V_T7_GPIO17_PE_EN(x) ((x) << S_T7_GPIO17_PE_EN)
+#define F_T7_GPIO17_PE_EN V_T7_GPIO17_PE_EN(1U)
+
+#define S_T7_GPIO16_PE_EN 16
+#define V_T7_GPIO16_PE_EN(x) ((x) << S_T7_GPIO16_PE_EN)
+#define F_T7_GPIO16_PE_EN V_T7_GPIO16_PE_EN(1U)
+
#define A_DBG_PVT_REG_THRESHOLD 0x611c
#define S_PVT_CALIBRATION_DONE 8
@@ -17859,6 +17881,22 @@
#define V_GPIO20_PS_EN(x) ((x) << S_GPIO20_PS_EN)
#define F_GPIO20_PS_EN V_GPIO20_PS_EN(1U)
+#define S_T7_GPIO19_PS_EN 19
+#define V_T7_GPIO19_PS_EN(x) ((x) << S_T7_GPIO19_PS_EN)
+#define F_T7_GPIO19_PS_EN V_T7_GPIO19_PS_EN(1U)
+
+#define S_T7_GPIO18_PS_EN 18
+#define V_T7_GPIO18_PS_EN(x) ((x) << S_T7_GPIO18_PS_EN)
+#define F_T7_GPIO18_PS_EN V_T7_GPIO18_PS_EN(1U)
+
+#define S_T7_GPIO17_PS_EN 17
+#define V_T7_GPIO17_PS_EN(x) ((x) << S_T7_GPIO17_PS_EN)
+#define F_T7_GPIO17_PS_EN V_T7_GPIO17_PS_EN(1U)
+
+#define S_T7_GPIO16_PS_EN 16
+#define V_T7_GPIO16_PS_EN(x) ((x) << S_T7_GPIO16_PS_EN)
+#define F_T7_GPIO16_PS_EN V_T7_GPIO16_PS_EN(1U)
+
#define A_DBG_PVT_REG_IN_TERMP 0x6120
#define S_REG_IN_TERMP_B 4
@@ -21825,10 +21863,6 @@
#define V_FUTURE_DEXPANSION_WTS(x) ((x) << S_FUTURE_DEXPANSION_WTS)
#define G_FUTURE_DEXPANSION_WTS(x) (((x) >> S_FUTURE_DEXPANSION_WTS) & M_FUTURE_DEXPANSION_WTS)
-#define S_T7_FUTURE_CEXPANSION_WTS 31
-#define V_T7_FUTURE_CEXPANSION_WTS(x) ((x) << S_T7_FUTURE_CEXPANSION_WTS)
-#define F_T7_FUTURE_CEXPANSION_WTS V_T7_FUTURE_CEXPANSION_WTS(1U)
-
#define S_CL14_WR_CMD_TO_ERROR 30
#define V_CL14_WR_CMD_TO_ERROR(x) ((x) << S_CL14_WR_CMD_TO_ERROR)
#define F_CL14_WR_CMD_TO_ERROR V_CL14_WR_CMD_TO_ERROR(1U)
@@ -21837,10 +21871,6 @@
#define V_CL13_WR_CMD_TO_ERROR(x) ((x) << S_CL13_WR_CMD_TO_ERROR)
#define F_CL13_WR_CMD_TO_ERROR V_CL13_WR_CMD_TO_ERROR(1U)
-#define S_T7_FUTURE_DEXPANSION_WTS 15
-#define V_T7_FUTURE_DEXPANSION_WTS(x) ((x) << S_T7_FUTURE_DEXPANSION_WTS)
-#define F_T7_FUTURE_DEXPANSION_WTS V_T7_FUTURE_DEXPANSION_WTS(1U)
-
#define S_CL14_WR_DATA_TO_ERROR 14
#define V_CL14_WR_DATA_TO_ERROR(x) ((x) << S_CL14_WR_DATA_TO_ERROR)
#define F_CL14_WR_DATA_TO_ERROR V_CL14_WR_DATA_TO_ERROR(1U)
@@ -21965,10 +21995,6 @@
#define V_FUTURE_DEXPANSION_RTE(x) ((x) << S_FUTURE_DEXPANSION_RTE)
#define G_FUTURE_DEXPANSION_RTE(x) (((x) >> S_FUTURE_DEXPANSION_RTE) & M_FUTURE_DEXPANSION_RTE)
-#define S_T7_FUTURE_CEXPANSION_RTE 31
-#define V_T7_FUTURE_CEXPANSION_RTE(x) ((x) << S_T7_FUTURE_CEXPANSION_RTE)
-#define F_T7_FUTURE_CEXPANSION_RTE V_T7_FUTURE_CEXPANSION_RTE(1U)
-
#define S_CL14_RD_CMD_TO_EN 30
#define V_CL14_RD_CMD_TO_EN(x) ((x) << S_CL14_RD_CMD_TO_EN)
#define F_CL14_RD_CMD_TO_EN V_CL14_RD_CMD_TO_EN(1U)
@@ -21977,10 +22003,6 @@
#define V_CL13_RD_CMD_TO_EN(x) ((x) << S_CL13_RD_CMD_TO_EN)
#define F_CL13_RD_CMD_TO_EN V_CL13_RD_CMD_TO_EN(1U)
-#define S_T7_FUTURE_DEXPANSION_RTE 15
-#define V_T7_FUTURE_DEXPANSION_RTE(x) ((x) << S_T7_FUTURE_DEXPANSION_RTE)
-#define F_T7_FUTURE_DEXPANSION_RTE V_T7_FUTURE_DEXPANSION_RTE(1U)
-
#define S_CL14_RD_DATA_TO_EN 14
#define V_CL14_RD_DATA_TO_EN(x) ((x) << S_CL14_RD_DATA_TO_EN)
#define F_CL14_RD_DATA_TO_EN V_CL14_RD_DATA_TO_EN(1U)
@@ -22105,10 +22127,6 @@
#define V_FUTURE_DEXPANSION_RTS(x) ((x) << S_FUTURE_DEXPANSION_RTS)
#define G_FUTURE_DEXPANSION_RTS(x) (((x) >> S_FUTURE_DEXPANSION_RTS) & M_FUTURE_DEXPANSION_RTS)
-#define S_T7_FUTURE_CEXPANSION_RTS 31
-#define V_T7_FUTURE_CEXPANSION_RTS(x) ((x) << S_T7_FUTURE_CEXPANSION_RTS)
-#define F_T7_FUTURE_CEXPANSION_RTS V_T7_FUTURE_CEXPANSION_RTS(1U)
-
#define S_CL14_RD_CMD_TO_ERROR 30
#define V_CL14_RD_CMD_TO_ERROR(x) ((x) << S_CL14_RD_CMD_TO_ERROR)
#define F_CL14_RD_CMD_TO_ERROR V_CL14_RD_CMD_TO_ERROR(1U)
@@ -22117,10 +22135,9 @@
#define V_CL13_RD_CMD_TO_ERROR(x) ((x) << S_CL13_RD_CMD_TO_ERROR)
#define F_CL13_RD_CMD_TO_ERROR V_CL13_RD_CMD_TO_ERROR(1U)
-#define S_T7_FUTURE_DEXPANSION_RTS 14
-#define M_T7_FUTURE_DEXPANSION_RTS 0x3U
-#define V_T7_FUTURE_DEXPANSION_RTS(x) ((x) << S_T7_FUTURE_DEXPANSION_RTS)
-#define G_T7_FUTURE_DEXPANSION_RTS(x) (((x) >> S_T7_FUTURE_DEXPANSION_RTS) & M_T7_FUTURE_DEXPANSION_RTS)
+#define S_CL14_RD_DATA_TO_ERROR 14
+#define V_CL14_RD_DATA_TO_ERROR(x) ((x) << S_CL14_RD_DATA_TO_ERROR)
+#define F_CL14_RD_DATA_TO_ERROR V_CL14_RD_DATA_TO_ERROR(1U)
#define S_CL13_RD_DATA_TO_ERROR 13
#define V_CL13_RD_DATA_TO_ERROR(x) ((x) << S_CL13_RD_DATA_TO_ERROR)
@@ -22224,10 +22241,9 @@
#define V_FUTURE_DEXPANSION_IPE(x) ((x) << S_FUTURE_DEXPANSION_IPE)
#define G_FUTURE_DEXPANSION_IPE(x) (((x) >> S_FUTURE_DEXPANSION_IPE) & M_FUTURE_DEXPANSION_IPE)
-#define S_T7_FUTURE_DEXPANSION_IPE 14
-#define M_T7_FUTURE_DEXPANSION_IPE 0x3ffffU
-#define V_T7_FUTURE_DEXPANSION_IPE(x) ((x) << S_T7_FUTURE_DEXPANSION_IPE)
-#define G_T7_FUTURE_DEXPANSION_IPE(x) (((x) >> S_T7_FUTURE_DEXPANSION_IPE) & M_T7_FUTURE_DEXPANSION_IPE)
+#define S_CL14_IF_PAR_EN 14
+#define V_CL14_IF_PAR_EN(x) ((x) << S_CL14_IF_PAR_EN)
+#define F_CL14_IF_PAR_EN V_CL14_IF_PAR_EN(1U)
#define S_CL13_IF_PAR_EN 13
#define V_CL13_IF_PAR_EN(x) ((x) << S_CL13_IF_PAR_EN)
@@ -22292,10 +22308,9 @@
#define V_FUTURE_DEXPANSION_IPS(x) ((x) << S_FUTURE_DEXPANSION_IPS)
#define G_FUTURE_DEXPANSION_IPS(x) (((x) >> S_FUTURE_DEXPANSION_IPS) & M_FUTURE_DEXPANSION_IPS)
-#define S_T7_FUTURE_DEXPANSION_IPS 14
-#define M_T7_FUTURE_DEXPANSION_IPS 0x3ffffU
-#define V_T7_FUTURE_DEXPANSION_IPS(x) ((x) << S_T7_FUTURE_DEXPANSION_IPS)
-#define G_T7_FUTURE_DEXPANSION_IPS(x) (((x) >> S_T7_FUTURE_DEXPANSION_IPS) & M_T7_FUTURE_DEXPANSION_IPS)
+#define S_CL14_IF_PAR_ERROR 14
+#define V_CL14_IF_PAR_ERROR(x) ((x) << S_CL14_IF_PAR_ERROR)
+#define F_CL14_IF_PAR_ERROR V_CL14_IF_PAR_ERROR(1U)
#define S_CL13_IF_PAR_ERROR 13
#define V_CL13_IF_PAR_ERROR(x) ((x) << S_CL13_IF_PAR_ERROR)
@@ -39030,21 +39045,21 @@
#define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028
#define A_PM_TX_PERR_ENABLE 0x10028
-#define S_T7_1_OSPI_OVERFLOW3 23
-#define V_T7_1_OSPI_OVERFLOW3(x) ((x) << S_T7_1_OSPI_OVERFLOW3)
-#define F_T7_1_OSPI_OVERFLOW3 V_T7_1_OSPI_OVERFLOW3(1U)
+#define S_OSPI_OVERFLOW3_TX 23
+#define V_OSPI_OVERFLOW3_TX(x) ((x) << S_OSPI_OVERFLOW3_TX)
+#define F_OSPI_OVERFLOW3_TX V_OSPI_OVERFLOW3_TX(1U)
-#define S_T7_1_OSPI_OVERFLOW2 22
-#define V_T7_1_OSPI_OVERFLOW2(x) ((x) << S_T7_1_OSPI_OVERFLOW2)
-#define F_T7_1_OSPI_OVERFLOW2 V_T7_1_OSPI_OVERFLOW2(1U)
+#define S_OSPI_OVERFLOW2_TX 22
+#define V_OSPI_OVERFLOW2_TX(x) ((x) << S_OSPI_OVERFLOW2_TX)
+#define F_OSPI_OVERFLOW2_TX V_OSPI_OVERFLOW2_TX(1U)
-#define S_T7_1_OSPI_OVERFLOW1 21
-#define V_T7_1_OSPI_OVERFLOW1(x) ((x) << S_T7_1_OSPI_OVERFLOW1)
-#define F_T7_1_OSPI_OVERFLOW1 V_T7_1_OSPI_OVERFLOW1(1U)
+#define S_OSPI_OVERFLOW1_TX 21
+#define V_OSPI_OVERFLOW1_TX(x) ((x) << S_OSPI_OVERFLOW1_TX)
+#define F_OSPI_OVERFLOW1_TX V_OSPI_OVERFLOW1_TX(1U)
-#define S_T7_1_OSPI_OVERFLOW0 20
-#define V_T7_1_OSPI_OVERFLOW0(x) ((x) << S_T7_1_OSPI_OVERFLOW0)
-#define F_T7_1_OSPI_OVERFLOW0 V_T7_1_OSPI_OVERFLOW0(1U)
+#define S_OSPI_OVERFLOW0_TX 20
+#define V_OSPI_OVERFLOW0_TX(x) ((x) << S_OSPI_OVERFLOW0_TX)
+#define F_OSPI_OVERFLOW0_TX V_OSPI_OVERFLOW0_TX(1U)
#define S_T7_BUNDLE_LEN_OVFL_EN 18
#define V_T7_BUNDLE_LEN_OVFL_EN(x) ((x) << S_T7_BUNDLE_LEN_OVFL_EN)
@@ -41390,15 +41405,65 @@
#define V_T7_BUBBLE(x) ((x) << S_T7_BUBBLE)
#define F_T7_BUBBLE V_T7_BUBBLE(1U)
-#define S_TXTOKENFIFO 15
-#define M_TXTOKENFIFO 0x3ffU
-#define V_TXTOKENFIFO(x) ((x) << S_TXTOKENFIFO)
-#define G_TXTOKENFIFO(x) (((x) >> S_TXTOKENFIFO) & M_TXTOKENFIFO)
+#define S_TX_TF_FIFO_PERR 19
+#define V_TX_TF_FIFO_PERR(x) ((x) << S_TX_TF_FIFO_PERR)
+#define F_TX_TF_FIFO_PERR V_TX_TF_FIFO_PERR(1U)
-#define S_PERR_TP2MPS_TFIFO 13
-#define M_PERR_TP2MPS_TFIFO 0x3U
-#define V_PERR_TP2MPS_TFIFO(x) ((x) << S_PERR_TP2MPS_TFIFO)
-#define G_PERR_TP2MPS_TFIFO(x) (((x) >> S_PERR_TP2MPS_TFIFO) & M_PERR_TP2MPS_TFIFO)
+#define S_TX_FIFO_PERR 18
+#define V_TX_FIFO_PERR(x) ((x) << S_TX_FIFO_PERR)
+#define F_TX_FIFO_PERR V_TX_FIFO_PERR(1U)
+
+#define S_NON_IPSEC_TX_FIFO3_PERR 17
+#define V_NON_IPSEC_TX_FIFO3_PERR(x) ((x) << S_NON_IPSEC_TX_FIFO3_PERR)
+#define F_NON_IPSEC_TX_FIFO3_PERR V_NON_IPSEC_TX_FIFO3_PERR(1U)
+
+#define S_NON_IPSEC_TX_FIFO2_PERR 16
+#define V_NON_IPSEC_TX_FIFO2_PERR(x) ((x) << S_NON_IPSEC_TX_FIFO2_PERR)
+#define F_NON_IPSEC_TX_FIFO2_PERR V_NON_IPSEC_TX_FIFO2_PERR(1U)
+
+#define S_NON_IPSEC_TX_FIFO1_PERR 15
+#define V_NON_IPSEC_TX_FIFO1_PERR(x) ((x) << S_NON_IPSEC_TX_FIFO1_PERR)
+#define F_NON_IPSEC_TX_FIFO1_PERR V_NON_IPSEC_TX_FIFO1_PERR(1U)
+
+#define S_NON_IPSEC_TX_FIFO0_PERR 14
+#define V_NON_IPSEC_TX_FIFO0_PERR(x) ((x) << S_NON_IPSEC_TX_FIFO0_PERR)
+#define F_NON_IPSEC_TX_FIFO0_PERR V_NON_IPSEC_TX_FIFO0_PERR(1U)
+
+#define S_TP2MPS_TX0 13
+#define V_TP2MPS_TX0(x) ((x) << S_TP2MPS_TX0)
+#define F_TP2MPS_TX0 V_TP2MPS_TX0(1U)
+
+#define S_CRYPTO2MPS_TX0 12
+#define V_CRYPTO2MPS_TX0(x) ((x) << S_CRYPTO2MPS_TX0)
+#define F_CRYPTO2MPS_TX0 V_CRYPTO2MPS_TX0(1U)
+
+#define S_TP2MPS_TX1 11
+#define V_TP2MPS_TX1(x) ((x) << S_TP2MPS_TX1)
+#define F_TP2MPS_TX1 V_TP2MPS_TX1(1U)
+
+#define S_CRYPTO2MPS_TX1 10
+#define V_CRYPTO2MPS_TX1(x) ((x) << S_CRYPTO2MPS_TX1)
+#define F_CRYPTO2MPS_TX1 V_CRYPTO2MPS_TX1(1U)
+
+#define S_TP2MPS_TX2 9
+#define V_TP2MPS_TX2(x) ((x) << S_TP2MPS_TX2)
+#define F_TP2MPS_TX2 V_TP2MPS_TX2(1U)
+
+#define S_CRYPTO2MPS_TX2 8
+#define V_CRYPTO2MPS_TX2(x) ((x) << S_CRYPTO2MPS_TX2)
+#define F_CRYPTO2MPS_TX2 V_CRYPTO2MPS_TX2(1U)
+
+#define S_TP2MPS_TX3 7
+#define V_TP2MPS_TX3(x) ((x) << S_TP2MPS_TX3)
+#define F_TP2MPS_TX3 V_TP2MPS_TX3(1U)
+
+#define S_CRYPTO2MPS_TX3 6
+#define V_CRYPTO2MPS_TX3(x) ((x) << S_CRYPTO2MPS_TX3)
+#define F_CRYPTO2MPS_TX3 V_CRYPTO2MPS_TX3(1U)
+
+#define S_NCSI2MPS 5
+#define V_NCSI2MPS(x) ((x) << S_NCSI2MPS)
+#define F_NCSI2MPS V_NCSI2MPS(1U)
#define A_MPS_TX_INT_CAUSE 0x9408
#define A_MPS_TX_NCSI2MPS_CNT 0x940c
@@ -41420,6 +41485,16 @@
#define V_BUBBLEERRINT(x) ((x) << S_BUBBLEERRINT)
#define F_BUBBLEERRINT V_BUBBLEERRINT(1U)
+#define S_TXTOKENFIFO 15
+#define M_TXTOKENFIFO 0x3ffU
+#define V_TXTOKENFIFO(x) ((x) << S_TXTOKENFIFO)
+#define G_TXTOKENFIFO(x) (((x) >> S_TXTOKENFIFO) & M_TXTOKENFIFO)
+
+#define S_PERR_TP2MPS_TFIFO 13
+#define M_PERR_TP2MPS_TFIFO 0x3U
+#define V_PERR_TP2MPS_TFIFO(x) ((x) << S_PERR_TP2MPS_TFIFO)
+#define G_PERR_TP2MPS_TFIFO(x) (((x) >> S_PERR_TP2MPS_TFIFO) & M_PERR_TP2MPS_TFIFO)
+
#define A_MPS_TX_PERR_INJECT 0x9414
#define S_MPSTXMEMSEL 1
@@ -42174,7 +42249,45 @@
#define A_MPS_TX_DBG_CNT 0x947c
#define A_MPS_TX_INT2_ENABLE 0x9498
+
+#define S_T7_TX_FIFO_PERR 4
+#define V_T7_TX_FIFO_PERR(x) ((x) << S_T7_TX_FIFO_PERR)
+#define F_T7_TX_FIFO_PERR V_T7_TX_FIFO_PERR(1U)
+
+#define S_NON_IPSEC_TX_FIFO3 3
+#define V_NON_IPSEC_TX_FIFO3(x) ((x) << S_NON_IPSEC_TX_FIFO3)
+#define F_NON_IPSEC_TX_FIFO3 V_NON_IPSEC_TX_FIFO3(1U)
+
+#define S_NON_IPSEC_TX_FIFO2 2
+#define V_NON_IPSEC_TX_FIFO2(x) ((x) << S_NON_IPSEC_TX_FIFO2)
+#define F_NON_IPSEC_TX_FIFO2 V_NON_IPSEC_TX_FIFO2(1U)
+
+#define S_NON_IPSEC_TX_FIFO1 1
+#define V_NON_IPSEC_TX_FIFO1(x) ((x) << S_NON_IPSEC_TX_FIFO1)
+#define F_NON_IPSEC_TX_FIFO1 V_NON_IPSEC_TX_FIFO1(1U)
+
+#define S_NON_IPSEC_TX_FIFO0 0
+#define V_NON_IPSEC_TX_FIFO0(x) ((x) << S_NON_IPSEC_TX_FIFO0)
+#define F_NON_IPSEC_TX_FIFO0 V_NON_IPSEC_TX_FIFO0(1U)
+
#define A_MPS_TX_INT2_CAUSE 0x949c
+
+#define S_T7_NON_IPSEC_TX_FIFO3_PERR 3
+#define V_T7_NON_IPSEC_TX_FIFO3_PERR(x) ((x) << S_T7_NON_IPSEC_TX_FIFO3_PERR)
+#define F_T7_NON_IPSEC_TX_FIFO3_PERR V_T7_NON_IPSEC_TX_FIFO3_PERR(1U)
+
+#define S_T7_NON_IPSEC_TX_FIFO2_PERR 2
+#define V_T7_NON_IPSEC_TX_FIFO2_PERR(x) ((x) << S_T7_NON_IPSEC_TX_FIFO2_PERR)
+#define F_T7_NON_IPSEC_TX_FIFO2_PERR V_T7_NON_IPSEC_TX_FIFO2_PERR(1U)
+
+#define S_T7_NON_IPSEC_TX_FIFO1_PERR 1
+#define V_T7_NON_IPSEC_TX_FIFO1_PERR(x) ((x) << S_T7_NON_IPSEC_TX_FIFO1_PERR)
+#define F_T7_NON_IPSEC_TX_FIFO1_PERR V_T7_NON_IPSEC_TX_FIFO1_PERR(1U)
+
+#define S_T7_NON_IPSEC_TX_FIFO0_PERR 0
+#define V_T7_NON_IPSEC_TX_FIFO0_PERR(x) ((x) << S_T7_NON_IPSEC_TX_FIFO0_PERR)
+#define F_T7_NON_IPSEC_TX_FIFO0_PERR V_T7_NON_IPSEC_TX_FIFO0_PERR(1U)
+
#define A_MPS_TX_PERR2_ENABLE 0x94a0
#define A_MPS_TX_INT3_ENABLE 0x94a4
#define A_MPS_TX_INT3_CAUSE 0x94a8
@@ -42307,6 +42420,12 @@
#define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT)
#define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
+
+#define S_T5_RXPP 29
+#define M_T5_RXPP 0x3U
+#define V_T5_RXPP(x) ((x) << S_T5_RXPP)
+#define G_T5_RXPP(x) (((x) >> S_T5_RXPP) & M_T5_RXPP)
+
#define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618
#define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c
@@ -42429,6 +42548,26 @@
#define V_T5_TXVF(x) ((x) << S_T5_TXVF)
#define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF)
+#define S_RXVF_CERR 12
+#define M_RXVF_CERR 0xfU
+#define V_RXVF_CERR(x) ((x) << S_RXVF_CERR)
+#define G_RXVF_CERR(x) (((x) >> S_RXVF_CERR) & M_RXVF_CERR)
+
+#define S_TXVF_CERR 8
+#define M_TXVF_CERR 0xfU
+#define V_TXVF_CERR(x) ((x) << S_TXVF_CERR)
+#define G_TXVF_CERR(x) (((x) >> S_TXVF_CERR) & M_TXVF_CERR)
+
+#define S_RXVF_PERR 5
+#define M_RXVF_PERR 0x7U
+#define V_RXVF_PERR(x) ((x) << S_RXVF_PERR)
+#define G_RXVF_PERR(x) (((x) >> S_RXVF_PERR) & M_RXVF_PERR)
+
+#define S_TXVF_PERR 0
+#define M_TXVF_PERR 0x1fU
+#define V_TXVF_PERR(x) ((x) << S_TXVF_PERR)
+#define G_TXVF_PERR(x) (((x) >> S_TXVF_PERR) & M_TXVF_PERR)
+
#define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4
#define A_MPS_STAT_PERR_ENABLE_SRAM1 0x96c8
#define A_MPS_STAT_STOP_UPD_BG 0x96cc
@@ -42641,6 +42780,10 @@
#define V_FILTMEM(x) ((x) << S_FILTMEM)
#define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM)
+#define S_T7_TRCPLERRENB 17
+#define V_T7_TRCPLERRENB(x) ((x) << S_T7_TRCPLERRENB)
+#define F_T7_TRCPLERRENB V_T7_TRCPLERRENB(1U)
+
#define S_T7_MISCPERR 16
#define V_T7_MISCPERR(x) ((x) << S_T7_MISCPERR)
#define F_T7_MISCPERR V_T7_MISCPERR(1U)
@@ -42814,11 +42957,6 @@
#define A_T7_MPS_TRC_FILTER_RUNT_CTL 0xa4a0
#define A_T7_MPS_TRC_FILTER_DROP 0xa4c0
#define A_T7_MPS_TRC_INT_ENABLE 0xa4e0
-
-#define S_T7_TRCPLERRENB 17
-#define V_T7_TRCPLERRENB(x) ((x) << S_T7_TRCPLERRENB)
-#define F_T7_TRCPLERRENB V_T7_TRCPLERRENB(1U)
-
#define A_T7_MPS_TRC_INT_CAUSE 0xa4e4
#define A_T7_MPS_TRC_TIMESTAMP_L 0xa4e8
#define A_T7_MPS_TRC_TIMESTAMP_H 0xa4ec
@@ -42885,13 +43023,72 @@
#define G_PERR_TF_IN_CTL(x) (((x) >> S_PERR_TF_IN_CTL) & M_PERR_TF_IN_CTL)
#define A_MPS_TRC_INT_ENABLE2 0xa4f4
-#define A_MPS_TRC_INT_CAUSE2 0xa4f8
-#define S_T7_TRC_TF_ECC 22
-#define M_T7_TRC_TF_ECC 0xffU
-#define V_T7_TRC_TF_ECC(x) ((x) << S_T7_TRC_TF_ECC)
-#define G_T7_TRC_TF_ECC(x) (((x) >> S_T7_TRC_TF_ECC) & M_T7_TRC_TF_ECC)
+#define S_TX2RX_DWN_CONV_PERR_PT3_CERR 16
+#define V_TX2RX_DWN_CONV_PERR_PT3_CERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT3_CERR)
+#define F_TX2RX_DWN_CONV_PERR_PT3_CERR V_TX2RX_DWN_CONV_PERR_PT3_CERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT2_CERR 15
+#define V_TX2RX_DWN_CONV_PERR_PT2_CERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT2_CERR)
+#define F_TX2RX_DWN_CONV_PERR_PT2_CERR V_TX2RX_DWN_CONV_PERR_PT2_CERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT1_CERR 14
+#define V_TX2RX_DWN_CONV_PERR_PT1_CERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT1_CERR)
+#define F_TX2RX_DWN_CONV_PERR_PT1_CERR V_TX2RX_DWN_CONV_PERR_PT1_CERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT0_CERR 13
+#define V_TX2RX_DWN_CONV_PERR_PT0_CERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT0_CERR)
+#define F_TX2RX_DWN_CONV_PERR_PT0_CERR V_TX2RX_DWN_CONV_PERR_PT0_CERR(1U)
+#define S_MPS2MAC_DWN_CONV_PERR_PT1_CERR 12
+#define V_MPS2MAC_DWN_CONV_PERR_PT1_CERR(x) ((x) << S_MPS2MAC_DWN_CONV_PERR_PT1_CERR)
+#define F_MPS2MAC_DWN_CONV_PERR_PT1_CERR V_MPS2MAC_DWN_CONV_PERR_PT1_CERR(1U)
+
+#define S_MPS2MAC_DWN_CONV_PERR_PT0_CERR 11
+#define V_MPS2MAC_DWN_CONV_PERR_PT0_CERR(x) ((x) << S_MPS2MAC_DWN_CONV_PERR_PT0_CERR)
+#define F_MPS2MAC_DWN_CONV_PERR_PT0_CERR V_MPS2MAC_DWN_CONV_PERR_PT0_CERR(1U)
+
+#define S_MAC2MPS_DWN_CONV_PERR_PT1_CERR 10
+#define V_MAC2MPS_DWN_CONV_PERR_PT1_CERR(x) ((x) << S_MAC2MPS_DWN_CONV_PERR_PT1_CERR)
+#define F_MAC2MPS_DWN_CONV_PERR_PT1_CERR V_MAC2MPS_DWN_CONV_PERR_PT1_CERR(1U)
+
+#define S_MAC2MPS_DWN_CONV_PERR_PT0_CERR 9
+#define V_MAC2MPS_DWN_CONV_PERR_PT0_CERR(x) ((x) << S_MAC2MPS_DWN_CONV_PERR_PT0_CERR)
+#define F_MAC2MPS_DWN_CONV_PERR_PT0_CERR V_MAC2MPS_DWN_CONV_PERR_PT0_CERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT3_PERR 8
+#define V_TX2RX_DWN_CONV_PERR_PT3_PERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT3_PERR)
+#define F_TX2RX_DWN_CONV_PERR_PT3_PERR V_TX2RX_DWN_CONV_PERR_PT3_PERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT2_PERR 7
+#define V_TX2RX_DWN_CONV_PERR_PT2_PERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT2_PERR)
+#define F_TX2RX_DWN_CONV_PERR_PT2_PERR V_TX2RX_DWN_CONV_PERR_PT2_PERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT1_PERR 6
+#define V_TX2RX_DWN_CONV_PERR_PT1_PERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT1_PERR)
+#define F_TX2RX_DWN_CONV_PERR_PT1_PERR V_TX2RX_DWN_CONV_PERR_PT1_PERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT0_PERR 5
+#define V_TX2RX_DWN_CONV_PERR_PT0_PERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT0_PERR)
+#define F_TX2RX_DWN_CONV_PERR_PT0_PERR V_TX2RX_DWN_CONV_PERR_PT0_PERR(1U)
+
+#define S_MAC2MPS_DWN_CONV_PERR_PT1_PERR 4
+#define V_MAC2MPS_DWN_CONV_PERR_PT1_PERR(x) ((x) << S_MAC2MPS_DWN_CONV_PERR_PT1_PERR)
+#define F_MAC2MPS_DWN_CONV_PERR_PT1_PERR V_MAC2MPS_DWN_CONV_PERR_PT1_PERR(1U)
+
+#define S_MAC2MPS_DWN_CONV_PERR_PT0_PERR 3
+#define V_MAC2MPS_DWN_CONV_PERR_PT0_PERR(x) ((x) << S_MAC2MPS_DWN_CONV_PERR_PT0_PERR)
+#define F_MAC2MPS_DWN_CONV_PERR_PT0_PERR V_MAC2MPS_DWN_CONV_PERR_PT0_PERR(1U)
+
+#define S_MPS2MAC_DWN_CONV_PERR_PT1_PERR 2
+#define V_MPS2MAC_DWN_CONV_PERR_PT1_PERR(x) ((x) << S_MPS2MAC_DWN_CONV_PERR_PT1_PERR)
+#define F_MPS2MAC_DWN_CONV_PERR_PT1_PERR V_MPS2MAC_DWN_CONV_PERR_PT1_PERR(1U)
+
+#define S_MPS2MAC_DWN_CONV_PERR_PT0_PERR 1
+#define V_MPS2MAC_DWN_CONV_PERR_PT0_PERR(x) ((x) << S_MPS2MAC_DWN_CONV_PERR_PT0_PERR)
+#define F_MPS2MAC_DWN_CONV_PERR_PT0_PERR V_MPS2MAC_DWN_CONV_PERR_PT0_PERR(1U)
+
+#define A_MPS_TRC_INT_CAUSE2 0xa4f8
#define A_MPS_CLS_CTL 0xd000
#define S_MEMWRITEFAULT 4
@@ -43743,9 +43940,9 @@
#define A_MPS_RX_CHMN_CNT 0x11070
#define A_MPS_CTL_STAT 0x11070
-#define S_T7_CTL 0
-#define V_T7_CTL(x) ((x) << S_T7_CTL)
-#define F_T7_CTL V_T7_CTL(1U)
+#define S_T7_MPS_CTL 0
+#define V_T7_MPS_CTL(x) ((x) << S_T7_MPS_CTL)
+#define F_T7_MPS_CTL V_T7_MPS_CTL(1U)
#define A_MPS_RX_PERR_INT_CAUSE 0x11074
@@ -43849,54 +44046,60 @@
#define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
#define F_T6_INT_ERR_INT V_T6_INT_ERR_INT(1U)
-#define S_MAC_IN_FIFO_768B 30
-#define V_MAC_IN_FIFO_768B(x) ((x) << S_MAC_IN_FIFO_768B)
-#define F_MAC_IN_FIFO_768B V_MAC_IN_FIFO_768B(1U)
-
-#define S_T7_1_INT_ERR_INT 29
-#define V_T7_1_INT_ERR_INT(x) ((x) << S_T7_1_INT_ERR_INT)
-#define F_T7_1_INT_ERR_INT V_T7_1_INT_ERR_INT(1U)
+#define S_T7_INT_ERR_INT 30
+#define V_T7_INT_ERR_INT(x) ((x) << S_T7_INT_ERR_INT)
+#define F_T7_INT_ERR_INT V_T7_INT_ERR_INT(1U)
#define S_FLOP_PERR 28
#define V_FLOP_PERR(x) ((x) << S_FLOP_PERR)
#define F_FLOP_PERR V_FLOP_PERR(1U)
-#define S_RPLC_MAP 13
-#define M_RPLC_MAP 0x1fU
-#define V_RPLC_MAP(x) ((x) << S_RPLC_MAP)
-#define G_RPLC_MAP(x) (((x) >> S_RPLC_MAP) & M_RPLC_MAP)
+#define S_MPS_RX_ATRB_MAP_PERR 23
+#define V_MPS_RX_ATRB_MAP_PERR(x) ((x) << S_MPS_RX_ATRB_MAP_PERR)
+#define F_MPS_RX_ATRB_MAP_PERR V_MPS_RX_ATRB_MAP_PERR(1U)
-#define S_TKN_RUNT_DROP_FIFO 12
-#define V_TKN_RUNT_DROP_FIFO(x) ((x) << S_TKN_RUNT_DROP_FIFO)
-#define F_TKN_RUNT_DROP_FIFO V_TKN_RUNT_DROP_FIFO(1U)
+#define S_RPLC_MAP_VNI_PERR 18
+#define M_RPLC_MAP_VNI_PERR 0x1fU
+#define V_RPLC_MAP_VNI_PERR(x) ((x) << S_RPLC_MAP_VNI_PERR)
+#define G_RPLC_MAP_VNI_PERR(x) (((x) >> S_RPLC_MAP_VNI_PERR) & M_RPLC_MAP_VNI_PERR)
-#define S_T7_PPM3 9
-#define M_T7_PPM3 0x7U
-#define V_T7_PPM3(x) ((x) << S_T7_PPM3)
-#define G_T7_PPM3(x) (((x) >> S_T7_PPM3) & M_T7_PPM3)
+#define S_RPLC_MAP_MCAST_PERR 13
+#define M_RPLC_MAP_MCAST_PERR 0x1fU
+#define V_RPLC_MAP_MCAST_PERR(x) ((x) << S_RPLC_MAP_MCAST_PERR)
+#define G_RPLC_MAP_MCAST_PERR(x) (((x) >> S_RPLC_MAP_MCAST_PERR) & M_RPLC_MAP_MCAST_PERR)
-#define S_T7_PPM2 6
-#define M_T7_PPM2 0x7U
-#define V_T7_PPM2(x) ((x) << S_T7_PPM2)
-#define G_T7_PPM2(x) (((x) >> S_T7_PPM2) & M_T7_PPM2)
+#define S_PPM3_PERR 9
+#define M_PPM3_PERR 0x7U
+#define V_PPM3_PERR(x) ((x) << S_PPM3_PERR)
+#define G_PPM3_PERR(x) (((x) >> S_PPM3_PERR) & M_PPM3_PERR)
-#define S_T7_PPM1 3
-#define M_T7_PPM1 0x7U
-#define V_T7_PPM1(x) ((x) << S_T7_PPM1)
-#define G_T7_PPM1(x) (((x) >> S_T7_PPM1) & M_T7_PPM1)
+#define S_PPM2_PERR 6
+#define M_PPM2_PERR 0x7U
+#define V_PPM2_PERR(x) ((x) << S_PPM2_PERR)
+#define G_PPM2_PERR(x) (((x) >> S_PPM2_PERR) & M_PPM2_PERR)
-#define S_T7_PPM0 0
-#define M_T7_PPM0 0x7U
-#define V_T7_PPM0(x) ((x) << S_T7_PPM0)
-#define G_T7_PPM0(x) (((x) >> S_T7_PPM0) & M_T7_PPM0)
+#define S_PPM1_PERR 3
+#define M_PPM1_PERR 0x7U
+#define V_PPM1_PERR(x) ((x) << S_PPM1_PERR)
+#define G_PPM1_PERR(x) (((x) >> S_PPM1_PERR) & M_PPM1_PERR)
+
+#define S_PPM0_PERR 0
+#define M_PPM0_PERR 0x7U
+#define V_PPM0_PERR(x) ((x) << S_PPM0_PERR)
+#define G_PPM0_PERR(x) (((x) >> S_PPM0_PERR) & M_PPM0_PERR)
#define A_MPS_RX_PERR_INT_ENABLE 0x11078
+#define A_MPS_RX_PERR_ENABLE 0x1107c
-#define S_T7_2_INT_ERR_INT 30
-#define V_T7_2_INT_ERR_INT(x) ((x) << S_T7_2_INT_ERR_INT)
-#define F_T7_2_INT_ERR_INT V_T7_2_INT_ERR_INT(1U)
+#define S_MPS_RX_ATRB_MA_PERRP 23
+#define V_MPS_RX_ATRB_MA_PERRP(x) ((x) << S_MPS_RX_ATRB_MA_PERRP)
+#define F_MPS_RX_ATRB_MA_PERRP V_MPS_RX_ATRB_MA_PERRP(1U)
+
+#define S_RPLC_MAP_VN_PERRI 18
+#define M_RPLC_MAP_VN_PERRI 0x1fU
+#define V_RPLC_MAP_VN_PERRI(x) ((x) << S_RPLC_MAP_VN_PERRI)
+#define G_RPLC_MAP_VN_PERRI(x) (((x) >> S_RPLC_MAP_VN_PERRI) & M_RPLC_MAP_VN_PERRI)
-#define A_MPS_RX_PERR_ENABLE 0x1107c
#define A_MPS_RX_PERR_INJECT 0x11080
#define A_MPS_RX_FUNC_INT_CAUSE 0x11084
@@ -43965,6 +44168,38 @@
#define V_LEN_ERR_INT(x) ((x) << S_LEN_ERR_INT)
#define F_LEN_ERR_INT V_LEN_ERR_INT(1U)
+#define S_MTU_ERR3 19
+#define V_MTU_ERR3(x) ((x) << S_MTU_ERR3)
+#define F_MTU_ERR3 V_MTU_ERR3(1U)
+
+#define S_MTU_ERR2 18
+#define V_MTU_ERR2(x) ((x) << S_MTU_ERR2)
+#define F_MTU_ERR2 V_MTU_ERR2(1U)
+
+#define S_MTU_ERR1 17
+#define V_MTU_ERR1(x) ((x) << S_MTU_ERR1)
+#define F_MTU_ERR1 V_MTU_ERR1(1U)
+
+#define S_MTU_ERR0 16
+#define V_MTU_ERR0(x) ((x) << S_MTU_ERR0)
+#define F_MTU_ERR0 V_MTU_ERR0(1U)
+
+#define S_DBG_LEN_ERR 15
+#define V_DBG_LEN_ERR(x) ((x) << S_DBG_LEN_ERR)
+#define F_DBG_LEN_ERR V_DBG_LEN_ERR(1U)
+
+#define S_DBG_SPI_ERR 14
+#define V_DBG_SPI_ERR(x) ((x) << S_DBG_SPI_ERR)
+#define F_DBG_SPI_ERR V_DBG_SPI_ERR(1U)
+
+#define S_DBG_SE_CNT_ERR 13
+#define V_DBG_SE_CNT_ERR(x) ((x) << S_DBG_SE_CNT_ERR)
+#define F_DBG_SE_CNT_ERR V_DBG_SE_CNT_ERR(1U)
+
+#define S_DBG_SPI_LEN_SE_CNT_ERR 12
+#define V_DBG_SPI_LEN_SE_CNT_ERR(x) ((x) << S_DBG_SPI_LEN_SE_CNT_ERR)
+#define F_DBG_SPI_LEN_SE_CNT_ERR V_DBG_SPI_LEN_SE_CNT_ERR(1U)
+
#define A_MPS_RX_FUNC_INT_ENABLE 0x11088
#define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c
@@ -43980,59 +44215,59 @@
#define A_MPS_RX_PERR_INT_CAUSE2 0x1108c
-#define S_CRYPT2MPS_RX_INTF_FIFO 28
-#define M_CRYPT2MPS_RX_INTF_FIFO 0xfU
-#define V_CRYPT2MPS_RX_INTF_FIFO(x) ((x) << S_CRYPT2MPS_RX_INTF_FIFO)
-#define G_CRYPT2MPS_RX_INTF_FIFO(x) (((x) >> S_CRYPT2MPS_RX_INTF_FIFO) & M_CRYPT2MPS_RX_INTF_FIFO)
+#define S_CRYPTO2MPS_RX0_PERR 31
+#define V_CRYPTO2MPS_RX0_PERR(x) ((x) << S_CRYPTO2MPS_RX0_PERR)
+#define F_CRYPTO2MPS_RX0_PERR V_CRYPTO2MPS_RX0_PERR(1U)
-#define S_INIC2MPS_TX0_PERR 27
-#define V_INIC2MPS_TX0_PERR(x) ((x) << S_INIC2MPS_TX0_PERR)
-#define F_INIC2MPS_TX0_PERR V_INIC2MPS_TX0_PERR(1U)
+#define S_CRYPTO2MPS_RX1_PERR 30
+#define V_CRYPTO2MPS_RX1_PERR(x) ((x) << S_CRYPTO2MPS_RX1_PERR)
+#define F_CRYPTO2MPS_RX1_PERR V_CRYPTO2MPS_RX1_PERR(1U)
+
+#define S_CRYPTO2MPS_RX2_PERR 29
+#define V_CRYPTO2MPS_RX2_PERR(x) ((x) << S_CRYPTO2MPS_RX2_PERR)
+#define F_CRYPTO2MPS_RX2_PERR V_CRYPTO2MPS_RX2_PERR(1U)
-#define S_INIC2MPS_TX1_PERR 26
+#define S_CRYPTO2MPS_RX3_PERR 28
+#define V_CRYPTO2MPS_RX3_PERR(x) ((x) << S_CRYPTO2MPS_RX3_PERR)
+#define F_CRYPTO2MPS_RX3_PERR V_CRYPTO2MPS_RX3_PERR(1U)
+
+#define S_INIC2MPS_TX1_PERR 27
#define V_INIC2MPS_TX1_PERR(x) ((x) << S_INIC2MPS_TX1_PERR)
#define F_INIC2MPS_TX1_PERR V_INIC2MPS_TX1_PERR(1U)
-#define S_XGMAC2MPS_RX0_PERR 25
-#define V_XGMAC2MPS_RX0_PERR(x) ((x) << S_XGMAC2MPS_RX0_PERR)
-#define F_XGMAC2MPS_RX0_PERR V_XGMAC2MPS_RX0_PERR(1U)
+#define S_INIC2MPS_TX0_PERR 26
+#define V_INIC2MPS_TX0_PERR(x) ((x) << S_INIC2MPS_TX0_PERR)
+#define F_INIC2MPS_TX0_PERR V_INIC2MPS_TX0_PERR(1U)
-#define S_XGMAC2MPS_RX1_PERR 24
+#define S_XGMAC2MPS_RX1_PERR 25
#define V_XGMAC2MPS_RX1_PERR(x) ((x) << S_XGMAC2MPS_RX1_PERR)
#define F_XGMAC2MPS_RX1_PERR V_XGMAC2MPS_RX1_PERR(1U)
-#define S_MPS2CRYPTO_RX_INTF_FIFO 20
-#define M_MPS2CRYPTO_RX_INTF_FIFO 0xfU
-#define V_MPS2CRYPTO_RX_INTF_FIFO(x) ((x) << S_MPS2CRYPTO_RX_INTF_FIFO)
-#define G_MPS2CRYPTO_RX_INTF_FIFO(x) (((x) >> S_MPS2CRYPTO_RX_INTF_FIFO) & M_MPS2CRYPTO_RX_INTF_FIFO)
-
-#define S_MAC_RX_PPROC_MPS2TP_TF 19
-#define V_MAC_RX_PPROC_MPS2TP_TF(x) ((x) << S_MAC_RX_PPROC_MPS2TP_TF)
-#define F_MAC_RX_PPROC_MPS2TP_TF V_MAC_RX_PPROC_MPS2TP_TF(1U)
-
-#define S_MAC_RX_PPROC_LB_CH3 18
-#define V_MAC_RX_PPROC_LB_CH3(x) ((x) << S_MAC_RX_PPROC_LB_CH3)
-#define F_MAC_RX_PPROC_LB_CH3 V_MAC_RX_PPROC_LB_CH3(1U)
+#define S_XGMAC2MPS_RX0_PERR 24
+#define V_XGMAC2MPS_RX0_PERR(x) ((x) << S_XGMAC2MPS_RX0_PERR)
+#define F_XGMAC2MPS_RX0_PERR V_XGMAC2MPS_RX0_PERR(1U)
-#define S_MAC_RX_PPROC_LB_CH2 17
-#define V_MAC_RX_PPROC_LB_CH2(x) ((x) << S_MAC_RX_PPROC_LB_CH2)
-#define F_MAC_RX_PPROC_LB_CH2 V_MAC_RX_PPROC_LB_CH2(1U)
+#define S_MPS2CRYPTO_CH0_INTF_FIFO_PERR 20
+#define M_MPS2CRYPTO_CH0_INTF_FIFO_PERR 0xfU
+#define V_MPS2CRYPTO_CH0_INTF_FIFO_PERR(x) ((x) << S_MPS2CRYPTO_CH0_INTF_FIFO_PERR)
+#define G_MPS2CRYPTO_CH0_INTF_FIFO_PERR(x) (((x) >> S_MPS2CRYPTO_CH0_INTF_FIFO_PERR) & M_MPS2CRYPTO_CH0_INTF_FIFO_PERR)
-#define S_MAC_RX_PPROC_LB_CH1 16
-#define V_MAC_RX_PPROC_LB_CH1(x) ((x) << S_MAC_RX_PPROC_LB_CH1)
-#define F_MAC_RX_PPROC_LB_CH1 V_MAC_RX_PPROC_LB_CH1(1U)
+#define S_RX_FINAL_TF_FIFO_PERR 19
+#define V_RX_FINAL_TF_FIFO_PERR(x) ((x) << S_RX_FINAL_TF_FIFO_PERR)
+#define F_RX_FINAL_TF_FIFO_PERR V_RX_FINAL_TF_FIFO_PERR(1U)
-#define S_MAC_RX_PPROC_LB_CH0 15
-#define V_MAC_RX_PPROC_LB_CH0(x) ((x) << S_MAC_RX_PPROC_LB_CH0)
-#define F_MAC_RX_PPROC_LB_CH0 V_MAC_RX_PPROC_LB_CH0(1U)
+#define S_MPS_LB_FIFO_PERR 15
+#define M_MPS_LB_FIFO_PERR 0xfU
+#define V_MPS_LB_FIFO_PERR(x) ((x) << S_MPS_LB_FIFO_PERR)
+#define G_MPS_LB_FIFO_PERR(x) (((x) >> S_MPS_LB_FIFO_PERR) & M_MPS_LB_FIFO_PERR)
-#define S_MAC_RX_PPROC_DWRR_CH0_3 14
-#define V_MAC_RX_PPROC_DWRR_CH0_3(x) ((x) << S_MAC_RX_PPROC_DWRR_CH0_3)
-#define F_MAC_RX_PPROC_DWRR_CH0_3 V_MAC_RX_PPROC_DWRR_CH0_3(1U)
+#define S_MPS_DWRR_FIFO_PERR 14
+#define V_MPS_DWRR_FIFO_PERR(x) ((x) << S_MPS_DWRR_FIFO_PERR)
+#define F_MPS_DWRR_FIFO_PERR V_MPS_DWRR_FIFO_PERR(1U)
-#define S_MAC_RX_FIFO_PERR 13
-#define V_MAC_RX_FIFO_PERR(x) ((x) << S_MAC_RX_FIFO_PERR)
-#define F_MAC_RX_FIFO_PERR V_MAC_RX_FIFO_PERR(1U)
+#define S_MAC_TF_FIFO_PERR 13
+#define V_MAC_TF_FIFO_PERR(x) ((x) << S_MAC_TF_FIFO_PERR)
+#define F_MAC_TF_FIFO_PERR V_MAC_TF_FIFO_PERR(1U)
#define S_MAC2MPS_PT3_PERR 12
#define V_MAC2MPS_PT3_PERR(x) ((x) << S_MAC2MPS_PT3_PERR)
@@ -44050,13 +44285,18 @@
#define V_MAC2MPS_PT0_PERR(x) ((x) << S_MAC2MPS_PT0_PERR)
#define F_MAC2MPS_PT0_PERR V_MAC2MPS_PT0_PERR(1U)
-#define S_LPBK_FIFO_PERR 8
-#define V_LPBK_FIFO_PERR(x) ((x) << S_LPBK_FIFO_PERR)
-#define F_LPBK_FIFO_PERR V_LPBK_FIFO_PERR(1U)
+#define S_TP_LPBK_FIFO_PERR 8
+#define V_TP_LPBK_FIFO_PERR(x) ((x) << S_TP_LPBK_FIFO_PERR)
+#define F_TP_LPBK_FIFO_PERR V_TP_LPBK_FIFO_PERR(1U)
-#define S_TP2MPS_TF_FIFO_PERR 7
-#define V_TP2MPS_TF_FIFO_PERR(x) ((x) << S_TP2MPS_TF_FIFO_PERR)
-#define F_TP2MPS_TF_FIFO_PERR V_TP2MPS_TF_FIFO_PERR(1U)
+#define S_TP_LPBK_TF_PERR 7
+#define V_TP_LPBK_TF_PERR(x) ((x) << S_TP_LPBK_TF_PERR)
+#define F_TP_LPBK_TF_PERR V_TP_LPBK_TF_PERR(1U)
+
+#define S_RSDV1 0
+#define M_RSDV1 0x7fU
+#define V_RSDV1(x) ((x) << S_RSDV1)
+#define G_RSDV1(x) (((x) >> S_RSDV1) & M_RSDV1)
#define A_MPS_RX_PAUSE_GEN_TH_1 0x11090
#define A_MPS_RX_PERR_INT_ENABLE2 0x11090
@@ -44978,67 +45218,407 @@
#define A_MPS_VF_RPLCT_MAP6 0x11308
#define A_MPS_VF_RPLCT_MAP7 0x1130c
#define A_MPS_RX_PERR_INT_CAUSE3 0x11310
+
+#define S_FIFO_REPL_CH3_CERR 28
+#define V_FIFO_REPL_CH3_CERR(x) ((x) << S_FIFO_REPL_CH3_CERR)
+#define F_FIFO_REPL_CH3_CERR V_FIFO_REPL_CH3_CERR(1U)
+
+#define S_FIFO_REPL_CH2_CERR 27
+#define V_FIFO_REPL_CH2_CERR(x) ((x) << S_FIFO_REPL_CH2_CERR)
+#define F_FIFO_REPL_CH2_CERR V_FIFO_REPL_CH2_CERR(1U)
+
+#define S_FIFO_REPL_CH1_CERR 26
+#define V_FIFO_REPL_CH1_CERR(x) ((x) << S_FIFO_REPL_CH1_CERR)
+#define F_FIFO_REPL_CH1_CERR V_FIFO_REPL_CH1_CERR(1U)
+
+#define S_FIFO_REPL_CH0_CERR 25
+#define V_FIFO_REPL_CH0_CERR(x) ((x) << S_FIFO_REPL_CH0_CERR)
+#define F_FIFO_REPL_CH0_CERR V_FIFO_REPL_CH0_CERR(1U)
+
+#define S_VLAN_FILTER_RAM_CERR 24
+#define V_VLAN_FILTER_RAM_CERR(x) ((x) << S_VLAN_FILTER_RAM_CERR)
+#define F_VLAN_FILTER_RAM_CERR V_VLAN_FILTER_RAM_CERR(1U)
+
+#define S_MPS_RX_TD_STAT_FIFO_PERR_CH3 23
+#define V_MPS_RX_TD_STAT_FIFO_PERR_CH3(x) ((x) << S_MPS_RX_TD_STAT_FIFO_PERR_CH3)
+#define F_MPS_RX_TD_STAT_FIFO_PERR_CH3 V_MPS_RX_TD_STAT_FIFO_PERR_CH3(1U)
+
+#define S_RPLCT_HDR_FIFO_IN_PERR_CH3 22
+#define V_RPLCT_HDR_FIFO_IN_PERR_CH3(x) ((x) << S_RPLCT_HDR_FIFO_IN_PERR_CH3)
+#define F_RPLCT_HDR_FIFO_IN_PERR_CH3 V_RPLCT_HDR_FIFO_IN_PERR_CH3(1U)
+
+#define S_ID_FIFO_IN_PERR_CH3 21
+#define V_ID_FIFO_IN_PERR_CH3(x) ((x) << S_ID_FIFO_IN_PERR_CH3)
+#define F_ID_FIFO_IN_PERR_CH3 V_ID_FIFO_IN_PERR_CH3(1U)
+
+#define S_DESC_HDR2_PERR_CH3 20
+#define V_DESC_HDR2_PERR_CH3(x) ((x) << S_DESC_HDR2_PERR_CH3)
+#define F_DESC_HDR2_PERR_CH3 V_DESC_HDR2_PERR_CH3(1U)
+
+#define S_FIFO_REPL_PERR_CH3 19
+#define V_FIFO_REPL_PERR_CH3(x) ((x) << S_FIFO_REPL_PERR_CH3)
+#define F_FIFO_REPL_PERR_CH3 V_FIFO_REPL_PERR_CH3(1U)
+
+#define S_MPS_RX_TD_PERR_CH3 18
+#define V_MPS_RX_TD_PERR_CH3(x) ((x) << S_MPS_RX_TD_PERR_CH3)
+#define F_MPS_RX_TD_PERR_CH3 V_MPS_RX_TD_PERR_CH3(1U)
+
+#define S_MPS_RX_TD_STAT_FIFO_PERR_CH2 17
+#define V_MPS_RX_TD_STAT_FIFO_PERR_CH2(x) ((x) << S_MPS_RX_TD_STAT_FIFO_PERR_CH2)
+#define F_MPS_RX_TD_STAT_FIFO_PERR_CH2 V_MPS_RX_TD_STAT_FIFO_PERR_CH2(1U)
+
+#define S_RPLCT_HDR_FIFO_IN_PERR_CH2 16
+#define V_RPLCT_HDR_FIFO_IN_PERR_CH2(x) ((x) << S_RPLCT_HDR_FIFO_IN_PERR_CH2)
+#define F_RPLCT_HDR_FIFO_IN_PERR_CH2 V_RPLCT_HDR_FIFO_IN_PERR_CH2(1U)
+
+#define S_ID_FIFO_IN_PERR_CH2 15
+#define V_ID_FIFO_IN_PERR_CH2(x) ((x) << S_ID_FIFO_IN_PERR_CH2)
+#define F_ID_FIFO_IN_PERR_CH2 V_ID_FIFO_IN_PERR_CH2(1U)
+
+#define S_DESC_HDR2_PERR_CH2 14
+#define V_DESC_HDR2_PERR_CH2(x) ((x) << S_DESC_HDR2_PERR_CH2)
+#define F_DESC_HDR2_PERR_CH2 V_DESC_HDR2_PERR_CH2(1U)
+
+#define S_FIFO_REPL_PERR_CH2 13
+#define V_FIFO_REPL_PERR_CH2(x) ((x) << S_FIFO_REPL_PERR_CH2)
+#define F_FIFO_REPL_PERR_CH2 V_FIFO_REPL_PERR_CH2(1U)
+
+#define S_MPS_RX_TD_PERR_CH2 12
+#define V_MPS_RX_TD_PERR_CH2(x) ((x) << S_MPS_RX_TD_PERR_CH2)
+#define F_MPS_RX_TD_PERR_CH2 V_MPS_RX_TD_PERR_CH2(1U)
+
+#define S_MPS_RX_TD_STAT_FIFO_PERR_CH1 11
+#define V_MPS_RX_TD_STAT_FIFO_PERR_CH1(x) ((x) << S_MPS_RX_TD_STAT_FIFO_PERR_CH1)
+#define F_MPS_RX_TD_STAT_FIFO_PERR_CH1 V_MPS_RX_TD_STAT_FIFO_PERR_CH1(1U)
+
+#define S_RPLCT_HDR_FIFO_IN_PERR_CH1 10
+#define V_RPLCT_HDR_FIFO_IN_PERR_CH1(x) ((x) << S_RPLCT_HDR_FIFO_IN_PERR_CH1)
+#define F_RPLCT_HDR_FIFO_IN_PERR_CH1 V_RPLCT_HDR_FIFO_IN_PERR_CH1(1U)
+
+#define S_ID_FIFO_IN_PERR_CH1 9
+#define V_ID_FIFO_IN_PERR_CH1(x) ((x) << S_ID_FIFO_IN_PERR_CH1)
+#define F_ID_FIFO_IN_PERR_CH1 V_ID_FIFO_IN_PERR_CH1(1U)
+
+#define S_DESC_HDR2_PERR_CH1 8
+#define V_DESC_HDR2_PERR_CH1(x) ((x) << S_DESC_HDR2_PERR_CH1)
+#define F_DESC_HDR2_PERR_CH1 V_DESC_HDR2_PERR_CH1(1U)
+
+#define S_FIFO_REPL_PERR_CH1 7
+#define V_FIFO_REPL_PERR_CH1(x) ((x) << S_FIFO_REPL_PERR_CH1)
+#define F_FIFO_REPL_PERR_CH1 V_FIFO_REPL_PERR_CH1(1U)
+
+#define S_MPS_RX_TD_PERR_CH1 6
+#define V_MPS_RX_TD_PERR_CH1(x) ((x) << S_MPS_RX_TD_PERR_CH1)
+#define F_MPS_RX_TD_PERR_CH1 V_MPS_RX_TD_PERR_CH1(1U)
+
+#define S_MPS_RX_TD_STAT_FIFO_PERR_CH0 5
+#define V_MPS_RX_TD_STAT_FIFO_PERR_CH0(x) ((x) << S_MPS_RX_TD_STAT_FIFO_PERR_CH0)
+#define F_MPS_RX_TD_STAT_FIFO_PERR_CH0 V_MPS_RX_TD_STAT_FIFO_PERR_CH0(1U)
+
+#define S_RPLCT_HDR_FIFO_IN_PERR_CH0 4
+#define V_RPLCT_HDR_FIFO_IN_PERR_CH0(x) ((x) << S_RPLCT_HDR_FIFO_IN_PERR_CH0)
+#define F_RPLCT_HDR_FIFO_IN_PERR_CH0 V_RPLCT_HDR_FIFO_IN_PERR_CH0(1U)
+
+#define S_ID_FIFO_IN_PERR_CH0 3
+#define V_ID_FIFO_IN_PERR_CH0(x) ((x) << S_ID_FIFO_IN_PERR_CH0)
+#define F_ID_FIFO_IN_PERR_CH0 V_ID_FIFO_IN_PERR_CH0(1U)
+
+#define S_DESC_HDR2_PERR_CH0 2
+#define V_DESC_HDR2_PERR_CH0(x) ((x) << S_DESC_HDR2_PERR_CH0)
+#define F_DESC_HDR2_PERR_CH0 V_DESC_HDR2_PERR_CH0(1U)
+
+#define S_FIFO_REPL_PERR_CH0 1
+#define V_FIFO_REPL_PERR_CH0(x) ((x) << S_FIFO_REPL_PERR_CH0)
+#define F_FIFO_REPL_PERR_CH0 V_FIFO_REPL_PERR_CH0(1U)
+
+#define S_MPS_RX_TD_PERR_CH0 0
+#define V_MPS_RX_TD_PERR_CH0(x) ((x) << S_MPS_RX_TD_PERR_CH0)
+#define F_MPS_RX_TD_PERR_CH0 V_MPS_RX_TD_PERR_CH0(1U)
+
#define A_MPS_RX_PERR_INT_ENABLE3 0x11314
#define A_MPS_RX_PERR_ENABLE3 0x11318
#define A_MPS_RX_PERR_INT_CAUSE4 0x1131c
-#define S_CLS 20
-#define M_CLS 0x3fU
-#define V_CLS(x) ((x) << S_CLS)
-#define G_CLS(x) (((x) >> S_CLS) & M_CLS)
+#define S_VNI_MULTICAST_FIFO_ECC_ERR_CH3 30
+#define V_VNI_MULTICAST_FIFO_ECC_ERR_CH3(x) ((x) << S_VNI_MULTICAST_FIFO_ECC_ERR_CH3)
+#define F_VNI_MULTICAST_FIFO_ECC_ERR_CH3 V_VNI_MULTICAST_FIFO_ECC_ERR_CH3(1U)
+
+#define S_VNI_MULTICAST_FIFO_ECC_ERR_CH2 29
+#define V_VNI_MULTICAST_FIFO_ECC_ERR_CH2(x) ((x) << S_VNI_MULTICAST_FIFO_ECC_ERR_CH2)
+#define F_VNI_MULTICAST_FIFO_ECC_ERR_CH2 V_VNI_MULTICAST_FIFO_ECC_ERR_CH2(1U)
+
+#define S_HASH_SRAM_CLS_ENG1 28
+#define V_HASH_SRAM_CLS_ENG1(x) ((x) << S_HASH_SRAM_CLS_ENG1)
+#define F_HASH_SRAM_CLS_ENG1 V_HASH_SRAM_CLS_ENG1(1U)
+
+#define S_HASH_SRAM_CLS_ENG0 27
+#define V_HASH_SRAM_CLS_ENG0(x) ((x) << S_HASH_SRAM_CLS_ENG0)
+#define F_HASH_SRAM_CLS_ENG0 V_HASH_SRAM_CLS_ENG0(1U)
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