git: a8c393384044 - main - arm64: Assume get_kernel_reg returns true
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Date: Mon, 09 Feb 2026 17:25:26 UTC
The branch main has been updated by andrew:
URL: https://cgit.FreeBSD.org/src/commit/?id=a8c3933840448eaf04ecfe162c0d05caf11090a4
commit a8c3933840448eaf04ecfe162c0d05caf11090a4
Author: Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2026-02-09 17:24:27 +0000
Commit: Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2026-02-09 17:24:27 +0000
arm64: Assume get_kernel_reg returns true
It now only returns true so this can be assumed and doesn't need to be
checked.
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D55105
---
sys/arm/arm/generic_timer.c | 7 +++----
sys/arm64/acpica/acpi_machdep.c | 6 +-----
sys/arm64/arm64/machdep.c | 6 ++----
sys/arm64/arm64/pmap.c | 21 +++++++++------------
sys/arm64/arm64/ptrauth.c | 15 ++++++---------
sys/arm64/arm64/vfp.c | 4 +---
sys/arm64/vmm/vmm.c | 5 ++---
sys/arm64/vmm/vmm_arm64.c | 39 +++++++++++++++++----------------------
sys/dev/hwpmc/hwpmc_arm64.c | 7 +++----
sys/dev/random/armv8rng.c | 4 ++--
sys/libkern/gsb_crc32.c | 7 +++----
11 files changed, 49 insertions(+), 72 deletions(-)
diff --git a/sys/arm/arm/generic_timer.c b/sys/arm/arm/generic_timer.c
index e3ba56a6f6ac..43e5d8b56531 100644
--- a/sys/arm/arm/generic_timer.c
+++ b/sys/arm/arm/generic_timer.c
@@ -662,8 +662,8 @@ arm_tmr_attach(device_t dev)
sc->get_cntxct = &get_cntxct;
#ifdef __aarch64__
- if (get_kernel_reg(ID_AA64MMFR0_EL1, &id_aa64mmfr0_el1) &&
- ID_AA64MMFR0_ECV_VAL(id_aa64mmfr0_el1) >= ID_AA64MMFR0_ECV_IMPL)
+ get_kernel_reg(ID_AA64MMFR0_EL1, &id_aa64mmfr0_el1);
+ if (ID_AA64MMFR0_ECV_VAL(id_aa64mmfr0_el1) >= ID_AA64MMFR0_ECV_IMPL)
sc->get_cntxct = &get_cntxctss;
#endif
#ifdef FDT
@@ -912,8 +912,7 @@ wfxt_check(const struct cpu_feat *feat __unused, u_int midr __unused)
{
uint64_t id_aa64isar2;
- if (!get_kernel_reg(ID_AA64ISAR2_EL1, &id_aa64isar2))
- return (FEAT_ALWAYS_DISABLE);
+ get_kernel_reg(ID_AA64ISAR2_EL1, &id_aa64isar2);
if (ID_AA64ISAR2_WFxT_VAL(id_aa64isar2) >= ID_AA64ISAR2_WFxT_IMPL)
return (FEAT_DEFAULT_ENABLE);
diff --git a/sys/arm64/acpica/acpi_machdep.c b/sys/arm64/acpica/acpi_machdep.c
index 123e5c328255..5ff875a98e53 100644
--- a/sys/arm64/acpica/acpi_machdep.c
+++ b/sys/arm64/acpica/acpi_machdep.c
@@ -235,11 +235,7 @@ parse_pxm_tables(void *dummy)
if (arm64_bus_method != ARM64_BUS_ACPI)
return;
- if (!get_kernel_reg(ID_AA64MMFR0_EL1, &mmfr0)) {
- /* chosen arbitrarily */
- mmfr0 = ID_AA64MMFR0_PARange_1T;
- }
-
+ get_kernel_reg(ID_AA64MMFR0_EL1, &mmfr0);
switch (ID_AA64MMFR0_PARange_VAL(mmfr0)) {
case ID_AA64MMFR0_PARange_4G:
parange = (vm_paddr_t)4 << 30 /* GiB */;
diff --git a/sys/arm64/arm64/machdep.c b/sys/arm64/arm64/machdep.c
index b1e22c900f3f..5e6a39381e84 100644
--- a/sys/arm64/arm64/machdep.c
+++ b/sys/arm64/arm64/machdep.c
@@ -178,8 +178,7 @@ pan_check(const struct cpu_feat *feat __unused, u_int midr __unused)
{
uint64_t id_aa64mfr1;
- if (!get_kernel_reg(ID_AA64MMFR1_EL1, &id_aa64mfr1))
- return (FEAT_ALWAYS_DISABLE);
+ get_kernel_reg(ID_AA64MMFR1_EL1, &id_aa64mfr1);
if (ID_AA64MMFR1_PAN_VAL(id_aa64mfr1) == ID_AA64MMFR1_PAN_NONE)
return (FEAT_ALWAYS_DISABLE);
@@ -224,8 +223,7 @@ mops_check(const struct cpu_feat *feat __unused, u_int midr __unused)
{
uint64_t id_aa64isar2;
- if (!get_kernel_reg(ID_AA64ISAR2_EL1, &id_aa64isar2))
- return (FEAT_ALWAYS_DISABLE);
+ get_kernel_reg(ID_AA64ISAR2_EL1, &id_aa64isar2);
if (ID_AA64ISAR2_MOPS_VAL(id_aa64isar2) == ID_AA64ISAR2_MOPS_NONE)
return (FEAT_ALWAYS_DISABLE);
diff --git a/sys/arm64/arm64/pmap.c b/sys/arm64/arm64/pmap.c
index dbf5c820d20b..680209efd881 100644
--- a/sys/arm64/arm64/pmap.c
+++ b/sys/arm64/arm64/pmap.c
@@ -9161,16 +9161,15 @@ pmap_init_mp(void *dummy __unused)
{
uint64_t reg;
- if (get_kernel_reg(ID_AA64PFR1_EL1, ®)) {
- if (ID_AA64PFR1_BT_VAL(reg) != ID_AA64PFR1_BT_NONE) {
- if (bootverbose)
- printf("Enabling BTI\n");
- pmap_bti_support = true;
+ get_kernel_reg(ID_AA64PFR1_EL1, ®);
+ if (ID_AA64PFR1_BT_VAL(reg) != ID_AA64PFR1_BT_NONE) {
+ if (bootverbose)
+ printf("Enabling BTI\n");
+ pmap_bti_support = true;
- pmap_bti_ranges_zone = uma_zcreate("BTI ranges",
- sizeof(struct rs_el), NULL, NULL, NULL, NULL,
- UMA_ALIGN_PTR, 0);
- }
+ pmap_bti_ranges_zone = uma_zcreate("BTI ranges",
+ sizeof(struct rs_el), NULL, NULL, NULL, NULL,
+ UMA_ALIGN_PTR, 0);
}
}
SYSINIT(pmap_init_mp, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_mp, NULL);
@@ -9185,9 +9184,7 @@ pmap_init_cnp(void *dummy __unused)
uint64_t reg;
u_int cpuid;
- if (!get_kernel_reg(ID_AA64MMFR2_EL1, ®))
- return;
-
+ get_kernel_reg(ID_AA64MMFR2_EL1, ®);
if (ID_AA64MMFR2_CnP_VAL(reg) != ID_AA64MMFR2_CnP_NONE) {
if (bootverbose)
printf("Enabling CnP\n");
diff --git a/sys/arm64/arm64/ptrauth.c b/sys/arm64/arm64/ptrauth.c
index ab40b72887e9..29f73db14e74 100644
--- a/sys/arm64/arm64/ptrauth.c
+++ b/sys/arm64/arm64/ptrauth.c
@@ -113,18 +113,15 @@ ptrauth_check(const struct cpu_feat *feat __unused, u_int midr __unused)
* The QARMA5 or implementation defined algorithms are reported in
* ID_AA64ISAR1_EL1.
*/
- if (get_kernel_reg(ID_AA64ISAR1_EL1, &isar)) {
- if (ID_AA64ISAR1_APA_VAL(isar) > 0 ||
- ID_AA64ISAR1_API_VAL(isar) > 0) {
- return (FEAT_DEFAULT_ENABLE);
- }
+ get_kernel_reg(ID_AA64ISAR1_EL1, &isar);
+ if (ID_AA64ISAR1_APA_VAL(isar) > 0 || ID_AA64ISAR1_API_VAL(isar) > 0) {
+ return (FEAT_DEFAULT_ENABLE);
}
/* The QARMA3 algorithm is reported in ID_AA64ISAR2_EL1. */
- if (get_kernel_reg(ID_AA64ISAR2_EL1, &isar)) {
- if (ID_AA64ISAR2_APA3_VAL(isar) > 0) {
- return (FEAT_DEFAULT_ENABLE);
- }
+ get_kernel_reg(ID_AA64ISAR2_EL1, &isar);
+ if (ID_AA64ISAR2_APA3_VAL(isar) > 0) {
+ return (FEAT_DEFAULT_ENABLE);
}
return (FEAT_ALWAYS_DISABLE);
diff --git a/sys/arm64/arm64/vfp.c b/sys/arm64/arm64/vfp.c
index 64f13458e2d9..d4c0eacf690c 100644
--- a/sys/arm64/arm64/vfp.c
+++ b/sys/arm64/arm64/vfp.c
@@ -895,9 +895,7 @@ sve_init(const void *dummy __unused)
uint64_t reg;
int i;
- if (!get_kernel_reg(ID_AA64PFR0_EL1, ®))
- return;
-
+ get_kernel_reg(ID_AA64PFR0_EL1, ®);
if (ID_AA64PFR0_SVE_VAL(reg) == ID_AA64PFR0_SVE_NONE)
return;
diff --git a/sys/arm64/vmm/vmm.c b/sys/arm64/vmm/vmm.c
index 031400f3f1d0..4231746e7eb2 100644
--- a/sys/arm64/vmm/vmm.c
+++ b/sys/arm64/vmm/vmm.c
@@ -154,9 +154,8 @@ vmm_regs_init(struct vmm_regs *regs, const struct vmm_regs *masks)
{
#define _FETCH_KERN_REG(reg, field) do { \
regs->field = vmm_arch_regs_masks.field; \
- if (!get_kernel_reg_iss_masked(reg ## _ISS, ®s->field, \
- masks->field)) \
- regs->field = 0; \
+ get_kernel_reg_iss_masked(reg ## _ISS, ®s->field, \
+ masks->field); \
} while (0)
_FETCH_KERN_REG(ID_AA64AFR0_EL1, id_aa64afr0);
_FETCH_KERN_REG(ID_AA64AFR1_EL1, id_aa64afr1);
diff --git a/sys/arm64/vmm/vmm_arm64.c b/sys/arm64/vmm/vmm_arm64.c
index 6643d32684d8..712783338214 100644
--- a/sys/arm64/vmm/vmm_arm64.c
+++ b/sys/arm64/vmm/vmm_arm64.c
@@ -251,10 +251,7 @@ vmmops_modinit(int ipinum)
return (ENODEV);
}
- if (!get_kernel_reg(ID_AA64MMFR0_EL1, &id_aa64mmfr0_el1)) {
- printf("vmm: Unable to read ID_AA64MMFR0_EL1\n");
- return (ENXIO);
- }
+ get_kernel_reg(ID_AA64MMFR0_EL1, &id_aa64mmfr0_el1);
pa_range_field = ID_AA64MMFR0_PARange_VAL(id_aa64mmfr0_el1);
/*
* Use 3 levels to give us up to 39 bits with 4k pages, or
@@ -522,27 +519,25 @@ vmmops_init(struct vm *vm, pmap_t pmap)
hyp->vm = vm;
hyp->vgic_attached = false;
- if (get_kernel_reg(ID_AA64MMFR0_EL1, &idreg)) {
- if (ID_AA64MMFR0_ECV_VAL(idreg) >= ID_AA64MMFR0_ECV_POFF)
- hyp->feats |= HYP_FEAT_ECV_POFF;
+ get_kernel_reg(ID_AA64MMFR0_EL1, &idreg);
+ if (ID_AA64MMFR0_ECV_VAL(idreg) >= ID_AA64MMFR0_ECV_POFF)
+ hyp->feats |= HYP_FEAT_ECV_POFF;
- switch (ID_AA64MMFR0_FGT_VAL(idreg)) {
- case ID_AA64MMFR0_FGT_NONE:
- break;
- default:
- case ID_AA64MMFR0_FGT_8_9:
- hyp->feats |= HYP_FEAT_FGT2;
- /* FALLTHROUGH */
- case ID_AA64MMFR0_FGT_8_6:
- hyp->feats |= HYP_FEAT_FGT;
- break;
- }
+ switch (ID_AA64MMFR0_FGT_VAL(idreg)) {
+ case ID_AA64MMFR0_FGT_NONE:
+ break;
+ default:
+ case ID_AA64MMFR0_FGT_8_9:
+ hyp->feats |= HYP_FEAT_FGT2;
+ /* FALLTHROUGH */
+ case ID_AA64MMFR0_FGT_8_6:
+ hyp->feats |= HYP_FEAT_FGT;
+ break;
}
- if (get_kernel_reg(ID_AA64MMFR1_EL1, &idreg)) {
- if (ID_AA64MMFR1_HCX_VAL(idreg) >= ID_AA64MMFR1_HCX_IMPL)
- hyp->feats |= HYP_FEAT_HCX;
- }
+ get_kernel_reg(ID_AA64MMFR1_EL1, &idreg);
+ if (ID_AA64MMFR1_HCX_VAL(idreg) >= ID_AA64MMFR1_HCX_IMPL)
+ hyp->feats |= HYP_FEAT_HCX;
vtimer_vminit(hyp);
vgic_vminit(hyp);
diff --git a/sys/dev/hwpmc/hwpmc_arm64.c b/sys/dev/hwpmc/hwpmc_arm64.c
index 310e43065716..794b285c0b3c 100644
--- a/sys/dev/hwpmc/hwpmc_arm64.c
+++ b/sys/dev/hwpmc/hwpmc_arm64.c
@@ -558,10 +558,9 @@ pmc_arm64_initialize(void)
snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr);
/* Check if we have 64-bit counters */
- if (get_kernel_reg(ID_AA64DFR0_EL1, &dfr)) {
- if (ID_AA64DFR0_PMUVer_VAL(dfr) >= ID_AA64DFR0_PMUVer_3_5)
- arm64_64bit_events = true;
- }
+ get_kernel_reg(ID_AA64DFR0_EL1, &dfr);
+ if (ID_AA64DFR0_PMUVer_VAL(dfr) >= ID_AA64DFR0_PMUVer_3_5)
+ arm64_64bit_events = true;
/*
* Allocate space for pointers to PMC HW descriptors and for
diff --git a/sys/dev/random/armv8rng.c b/sys/dev/random/armv8rng.c
index 9573c09aa77a..7aa6f4b0ded1 100644
--- a/sys/dev/random/armv8rng.c
+++ b/sys/dev/random/armv8rng.c
@@ -98,8 +98,8 @@ rndr_modevent(module_t mod, int type, void *unused)
switch (type) {
case MOD_LOAD:
has_rndr = false;
- if (get_kernel_reg(ID_AA64ISAR0_EL1, ®) &&
- ID_AA64ISAR0_RNDR_VAL(reg) != ID_AA64ISAR0_RNDR_NONE) {
+ get_kernel_reg(ID_AA64ISAR0_EL1, ®);
+ if (ID_AA64ISAR0_RNDR_VAL(reg) != ID_AA64ISAR0_RNDR_NONE) {
has_rndr = true;
random_source_register(&random_armv8_rndr);
printf("random: fast provider: \"%s\"\n",
diff --git a/sys/libkern/gsb_crc32.c b/sys/libkern/gsb_crc32.c
index 8cfee97d8d55..ab8c13d3023c 100644
--- a/sys/libkern/gsb_crc32.c
+++ b/sys/libkern/gsb_crc32.c
@@ -764,10 +764,9 @@ DEFINE_IFUNC(, uint32_t, calculate_crc32c,
{
uint64_t reg;
- if (get_kernel_reg(ID_AA64ISAR0_EL1, ®)) {
- if (ID_AA64ISAR0_CRC32_VAL(reg) >= ID_AA64ISAR0_CRC32_BASE)
- return (armv8_crc32c);
- }
+ get_kernel_reg(ID_AA64ISAR0_EL1, ®);
+ if (ID_AA64ISAR0_CRC32_VAL(reg) >= ID_AA64ISAR0_CRC32_BASE)
+ return (armv8_crc32c);
return (table_crc32c);
}