git: 2f5ed51b8528 - main - arm64: Add the GICv5 virtualisation register and struct definitions
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Date: Mon, 24 Aug 2026 14:46:28 UTC
The branch main has been updated by andrew:
URL: https://cgit.FreeBSD.org/src/commit/?id=2f5ed51b8528db8d5555b4fc0009f9991c28454b
commit 2f5ed51b8528db8d5555b4fc0009f9991c28454b
Author: Sarah Walker <sarah.walker2@arm.com>
AuthorDate: 2026-07-31 10:43:34 +0000
Commit: Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2026-08-24 14:45:18 +0000
arm64: Add the GICv5 virtualisation register and struct definitions
Co-developed-by: Andrew Turner <andrew@FreeBSD.org>
Sponsored by: Arm Ltd
---
sys/arm64/arm64/gicv5.c | 4 +-
sys/arm64/arm64/gicv5reg.h | 365 ++++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 365 insertions(+), 4 deletions(-)
diff --git a/sys/arm64/arm64/gicv5.c b/sys/arm64/arm64/gicv5.c
index 5201248e20f5..a533baacf489 100644
--- a/sys/arm64/arm64/gicv5.c
+++ b/sys/arm64/arm64/gicv5.c
@@ -483,7 +483,7 @@ gicv5_irs_attach(device_t dev, struct gicv5_irs *irs, u_int idx)
idr2 = IRS_CFG_READ_4(irs, IRS_IDR2);
- two_levels = (idr2 & IRS_IDR2_IST_LEVELS) != 0;
+ two_levels = (idr2 & IRS_IDR2_IST_LEVELS_TWO) != 0;
lpi_id_bits = IRS_IDR2_ID_BITS(idr2);
if (!two_levels) {
@@ -508,7 +508,7 @@ gicv5_irs_attach(device_t dev, struct gicv5_irs *irs, u_int idx)
}
/* The IST entries contain metadata so the size will be larger */
- if ((idr2 & IRS_IRD2_ISTMD) != 0) {
+ if ((idr2 & IRS_IDR2_ISTMD) != 0) {
uint64_t istmd_sz;
istmd_sz = (idr2 & IRS_IDR2_ISTMD_SZ_MASK) >>
diff --git a/sys/arm64/arm64/gicv5reg.h b/sys/arm64/arm64/gicv5reg.h
index a4cd7aa71bbc..942fd788f88f 100644
--- a/sys/arm64/arm64/gicv5reg.h
+++ b/sys/arm64/arm64/gicv5reg.h
@@ -205,6 +205,80 @@
#define GICR_CDNMIA_CRm 3
#define GICR_CDNMIA_op2 1
+/*
+ * GIC VDAFF, <Xt>
+ * Interrupt Set Target in the Current Interrupt Domain
+ */
+#define GIC_VDAFF MRS_REG_ALT_NAME(GIC_VDAFF)
+#define GIC_VDAFF_op0 1
+#define GIC_VDAFF_op1 4
+#define GIC_VDAFF_CRn 12
+#define GIC_VDAFF_CRm 1
+#define GIC_VDAFF_op2 3
+
+/*
+ * GIC VDEN, <Xt>
+ * Interrupt Enable in the Virtual Interrupt Domain
+ */
+#define GIC_VDEN MRS_REG_ALT_NAME(GIC_VDEN)
+#define GIC_VDEN_op0 1
+#define GIC_VDEN_op1 4
+#define GIC_VDEN_CRn 12
+#define GIC_VDEN_CRm 1
+#define GIC_VDEN_op2 1
+#define GIC_VDEN_TYPE_SHIFT 29
+#define GIC_VDEN_TYPE_WIDTH 3
+#define GIC_VDEN_TYPE_MASK (UL(0x7) << GIC_VDEN_TYPE_SHIFT)
+#define GIC_VDEN_TYPE_LPI (UL(0x2) << GIC_VDEN_TYPE_SHIFT)
+#define GIC_VDEN_TYPE_SPI (UL(0x3) << GIC_VDEN_TYPE_SHIFT)
+#define GIC_VDEN_ID_SHIFT 0
+#define GIC_VDEN_ID_WIDTH 24
+#define GIC_VDEN_ID_MASK (UL(0xffffff) << GIC_VDEN_ID_SHIFT)
+
+/*
+ * GIC VDPEND, <Xt>
+ * Interrupt Set/Clear Pending state in the Virtual Interrupt Domain
+ */
+#define GIC_VDPEND MRS_REG_ALT_NAME(GIC_VDPEND)
+#define GIC_VDPEND_op0 1
+#define GIC_VDPEND_op1 4
+#define GIC_VDPEND_CRn 12
+#define GIC_VDPEND_CRm 1
+#define GIC_VDPEND_op2 4
+#define GIC_VDPEND_PENDING (UL(0x1) << 63)
+#define GIC_VDPEND_VM_SHIFT 32
+#define GIC_VDPEND_VM_MASK (UL(0xffff) << GIC_VDPEND_VM_SHIFT)
+#define GIC_VDPEND_TYPE_SHIFT 29
+#define GIC_VDPEND_TYPE_WIDTH 3
+#define GIC_VDPEND_TYPE_MASK (UL(0x7) << GIC_VDPEND_TYPE_SHIFT)
+#define GIC_VDPEND_TYPE_LPI (UL(0x2) << GIC_VDPEND_TYPE_SHIFT)
+#define GIC_VDPEND_TYPE_SPI (UL(0x3) << GIC_VDPEND_TYPE_SHIFT)
+#define GIC_VDPEND_ID_SHIFT 0
+#define GIC_VDPEND_ID_WIDTH 24
+#define GIC_VDPEND_ID_MASK (UL(0xffffff) << GIC_VDPEND_ID_SHIFT)
+
+/*
+ * GIC VDPRI, <Xt>
+ * Interrupt Set priority in the Virtual Interrupt Domain
+ */
+#define GIC_VDPRI MRS_REG_ALT_NAME(GIC_VDPRI)
+#define GIC_VDPRI_op0 1
+#define GIC_VDPRI_op1 4
+#define GIC_VDPRI_CRn 12
+#define GIC_VDPRI_CRm 1
+#define GIC_VDPRI_op2 2
+
+/*
+ * GIC VDRCFG, <Xt>
+ *
+ */
+#define GIC_VDRCFG MRS_REG_ALT_NAME(GIC_VDRCFG)
+#define GIC_VDRCFG_op0 1
+#define GIC_VDRCFG_op1 4
+#define GIC_VDRCFG_CRn 12
+#define GIC_VDRCFG_CRm 1
+#define GIC_VDRCFG_op2 5
+
/*
* GSB ACK
* GIC Synchronization Barrier Interrupt Acknowledge
@@ -332,13 +406,18 @@
* Interrupt Controller ID Register 0
*/
#define ICC_IDR0_EL1 MRS_REG_ALT_NAME(ICC_IDR0_EL1)
+#define ICC_IDR0_EL1_ISS ISS_MSR_REG(ICC_IDR0_EL1)
#define ICC_IDR0_EL1_op0 3
#define ICC_IDR0_EL1_op1 0
#define ICC_IDR0_EL1_CRn 12
#define ICC_IDR0_EL1_CRm 10
#define ICC_IDR0_EL1_op2 2
#define ICC_IDR0_GCIE_LEGACY_SHIFT 8
+#define ICC_IDR0_GCIE_LEGACY_WIDTH 4
#define ICC_IDR0_GCIE_LEGACY_MASK (0xful << ICC_IDR0_GCIE_LEGACY_SHIFT)
+#define ICC_IDR0_GCIE_LEGACY_VAL(x) ((x) & ICC_IDR0_GCIE_LEGACY_MASK)
+#define ICC_IDR0_GCIE_LEGACY_NONE (UL(0x0) << ICC_IDR0_GCIE_LEGACY_SHIFT)
+#define ICC_IDR0_GCIE_LEGACY_IMPL (UL(0x1) << ICC_IDR0_GCIE_LEGACY_SHIFT)
#define ICC_IDR0_PRI_BITS_SHIFT 4
#define ICC_IDR0_PRI_BITS_MASK (0xful << ICC_IDR0_PRI_BITS_SHIFT)
#define ICC_IDR0_PRI_BITS_4 (0x3ul << ICC_IDR0_PRI_BITS_SHIFT)
@@ -513,10 +592,216 @@
#define ICC_PPI_SPENDR1_EL1_CRm 13
#define ICC_PPI_SPENDR1_EL1_op2 7
+/*
+ * Hypervisor control registers
+ */
+
+/*
+ * ICH_APR_EL2
+ * Interrupt Controller Virtual Active Priorities Register
+ */
+#define ICH_APR_EL2 MRS_REG_ALT_NAME(ICH_APR_EL2)
+#define ICH_APR_EL2_op0 3
+#define ICH_APR_EL2_op1 4
+#define ICH_APR_EL2_CRn 12
+#define ICH_APR_EL2_CRm 8
+#define ICH_APR_EL2_op2 4
+#define ICH_APR_P(x) (1ul << (x))
+
+/*
+ * ICH_CONTEXTR_EL2
+ * Interrupt Control Virtual Context Register
+ */
+#define ICH_CONTEXTR_EL2 MRS_REG_ALT_NAME(ICH_CONTEXTR_EL2)
+#define ICH_CONTEXTR_EL2_op0 3
+#define ICH_CONTEXTR_EL2_op1 4
+#define ICH_CONTEXTR_EL2_CRn 12
+#define ICH_CONTEXTR_EL2_CRm 11
+#define ICH_CONTEXTR_EL2_op2 6
+#define ICH_CONTEXTR_EL2_V (1ul << 63)
+#define ICH_CONTEXTR_EL2_F (1ul << 62)
+#define ICH_CONTEXTR_EL2_IRICHPPIDIS (1ul << 61)
+#define ICH_CONTEXTR_EL2_DB (1ul << 60)
+#define ICH_CONTEXTR_EL2_DBPM_SHIFT 55
+#define ICH_CONTEXTR_EL2_DBPM_MASK (0x1ful << ICH_CONTEXTR_EL2_DBPM_SHIFT)
+#define ICH_CONTEXTR_EL2_VPE_SHIFT 32
+#define ICH_CONTEXTR_EL2_VPE_MASK (0xfffful << ICH_CONTEXTR_EL2_VPE_SHIFT)
+#define ICH_CONTEXTR_EL2_VM_SHIFT 0
+#define ICH_CONTEXTR_EL2_VM_MASK (0xfffful << ICH_CONTEXTR_EL2_VM_SHIFT)
+
+
+/*
+ * ICH_HFGITR_EL2
+ * Hypervisor GIC Fine-Grained Read Trap Register
+ */
+#define ICH_HFGITR_EL2 MRS_REG_ALT_NAME(ICH_HFGITR_EL2)
+#define ICH_HFGITR_EL2_op0 3
+#define ICH_HFGITR_EL2_op1 4
+#define ICH_HFGITR_EL2_CRn 12
+#define ICH_HFGITR_EL2_CRm 9
+#define ICH_HFGITR_EL2_op2 7
+#define ICH_HFGITR_EL2_GICRCDNMIA (0x1ul << 10)
+#define ICH_HFGITR_EL2_GICRCDIA (0x1ul << 9)
+#define ICH_HFGITR_EL2_GICCDDI (0x1ul << 8)
+#define ICH_HFGITR_EL2_GICCDEOI (0x1ul << 7)
+#define ICH_HFGITR_EL2_GICCDHM (0x1ul << 6)
+#define ICH_HFGITR_EL2_GICCDRCFG (0x1ul << 5)
+#define ICH_HFGITR_EL2_GICCDPEND (0x1ul << 4)
+#define ICH_HFGITR_EL2_GICCDAFF (0x1ul << 3)
+#define ICH_HFGITR_EL2_GICCDPRI (0x1ul << 2)
+#define ICH_HFGITR_EL2_GICCDDIS (0x1ul << 1)
+#define ICH_HFGITR_EL2_GICCDEN (0x1ul << 0)
+
+/*
+ * ICH_HFGRTR_EL2
+ * Hypervisor GIC Fine-Grained Read Trap Register
+ */
+#define ICH_HFGRTR_EL2 MRS_REG_ALT_NAME(ICH_HFGRTR_EL2)
+#define ICH_HFGRTR_EL2_op0 3
+#define ICH_HFGRTR_EL2_op1 4
+#define ICH_HFGRTR_EL2_CRn 12
+#define ICH_HFGRTR_EL2_CRm 9
+#define ICH_HFGRTR_EL2_op2 4
+
+/*
+ * ICH_HFGWTR_EL2
+ * Hypervisor GIC Fine-Grained Write Trap Register
+ */
+#define ICH_HFGWTR_EL2 MRS_REG_ALT_NAME(ICH_HFGWTR_EL2)
+#define ICH_HFGWTR_EL2_op0 3
+#define ICH_HFGWTR_EL2_op1 4
+#define ICH_HFGWTR_EL2_CRn 12
+#define ICH_HFGWTR_EL2_CRm 9
+#define ICH_HFGWTR_EL2_op2 6
+
+/*
+ * ICH_HPPIR_EL2
+ * Hypervisor Highest Priority Pending Interrupt Register
+ */
+#define ICH_HPPIR_EL2 MRS_REG_ALT_NAME(ICH_HPPIR_EL2)
+#define ICH_HPPIR_EL2_op0 3
+#define ICH_HPPIR_EL2_op1 4
+#define ICH_HPPIR_EL2_CRn 12
+#define ICH_HPPIR_EL2_CRm 8
+#define ICH_HPPIR_EL2_op2 5
+#define ICH_HPPIR_EL2_HPPIV (0x1ul << 32)
+#define ICH_HPPIR_EL2_TYPE_SHIFT 29
+#define ICH_HPPIR_EL2_TYPE_MASK (0x7ul << ICH_HPPIR_EL2_TYPE_SHIFT)
+#define ICH_HPPIR_EL2_ID_SHIFT 0
+#define ICH_HPPIR_EL2_ID_MASK (0xfffffful << ICH_HPPIR_EL2_ID_SHIFT)
+
+/*
+ * ICH_PPI_ACTIVER<n>_EL2
+ * Interrupt Controller Virtual Interrupt Active Registers
+ */
+#define ICH_PPI_ACTIVER0_EL2 MRS_REG_ALT_NAME(ICH_PPI_ACTIVER0_EL2)
+#define ICH_PPI_ACTIVER0_EL2_op0 3
+#define ICH_PPI_ACTIVER0_EL2_op1 4
+#define ICH_PPI_ACTIVER0_EL2_CRn 12
+#define ICH_PPI_ACTIVER0_EL2_CRm 10
+#define ICH_PPI_ACTIVER0_EL2_op2 6
+
+#define ICH_PPI_ACTIVER1_EL2 MRS_REG_ALT_NAME(ICH_PPI_ACTIVER1_EL2)
+#define ICH_PPI_ACTIVER1_EL2_op0 3
+#define ICH_PPI_ACTIVER1_EL2_op1 4
+#define ICH_PPI_ACTIVER1_EL2_CRn 12
+#define ICH_PPI_ACTIVER1_EL2_CRm 10
+#define ICH_PPI_ACTIVER1_EL2_op2 7
+
+/*
+ * ICH_PPI_DVIR<n>_EL2
+ * Interrupt Controller PPI Direct-inject Virtual Interrupt Registers
+ */
+#define ICH_PPI_DVIR0_EL2 MRS_REG_ALT_NAME(ICH_PPI_DVIR0_EL2)
+#define ICH_PPI_DVIR0_EL2_op0 3
+#define ICH_PPI_DVIR0_EL2_op1 4
+#define ICH_PPI_DVIR0_EL2_CRn 12
+#define ICH_PPI_DVIR0_EL2_CRm 10
+#define ICH_PPI_DVIR0_EL2_op2 0
+
+#define ICH_PPI_DVIR1_EL2 MRS_REG_ALT_NAME(ICH_PPI_DVIR1_EL2)
+#define ICH_PPI_DVIR1_EL2_op0 3
+#define ICH_PPI_DVIR1_EL2_op1 4
+#define ICH_PPI_DVIR1_EL2_CRn 12
+#define ICH_PPI_DVIR1_EL2_CRm 10
+#define ICH_PPI_DVIR1_EL2_op2 1
+
+/*
+ * ICH_PPI_ENABLER<n>_EL2
+ * Interrupt Controller Virtual Interrupt Enable Registers
+ */
+#define ICH_PPI_ENABLER0_EL2 MRS_REG_ALT_NAME(ICH_PPI_ENABLER0_EL2)
+#define ICH_PPI_ENABLER0_EL2_op0 3
+#define ICH_PPI_ENABLER0_EL2_op1 4
+#define ICH_PPI_ENABLER0_EL2_CRn 12
+#define ICH_PPI_ENABLER0_EL2_CRm 10
+#define ICH_PPI_ENABLER0_EL2_op2 2
+
+#define ICH_PPI_ENABLER1_EL2 MRS_REG_ALT_NAME(ICH_PPI_ENABLER1_EL2)
+#define ICH_PPI_ENABLER1_EL2_op0 3
+#define ICH_PPI_ENABLER1_EL2_op1 4
+#define ICH_PPI_ENABLER1_EL2_CRn 12
+#define ICH_PPI_ENABLER1_EL2_CRm 10
+#define ICH_PPI_ENABLER1_EL2_op2 3
+
+/*
+ * ICH_PPI_PENDR<.>_EL2
+ * Interrupt Controller Virtual Interrupt Pending State Registers
+ */
+#define ICH_PPI_PENDR0_EL2 MRS_REG_ALT_NAME(ICH_PPI_PENDR0_EL2)
+#define ICH_PPI_PENDR0_EL2_op0 3
+#define ICH_PPI_PENDR0_EL2_op1 4
+#define ICH_PPI_PENDR0_EL2_CRn 12
+#define ICH_PPI_PENDR0_EL2_CRm 10
+#define ICH_PPI_PENDR0_EL2_op2 4
+
+#define ICH_PPI_PENDR1_EL2 MRS_REG_ALT_NAME(ICH_PPI_PENDR1_EL2)
+#define ICH_PPI_PENDR1_EL2_op0 3
+#define ICH_PPI_PENDR1_EL2_op1 4
+#define ICH_PPI_PENDR1_EL2_CRn 12
+#define ICH_PPI_PENDR1_EL2_CRm 10
+#define ICH_PPI_PENDR1_EL2_op2 5
+
+/*
+ * ICH_PPI_PRIORITYR_EL2
+ * Interrupt Controller Virtual Interrupt Priority Registers
+ */
+#define ICH_PPI_PRIORITYR0_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 14, 0)
+#define ICH_PPI_PRIORITYR1_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 14, 1)
+#define ICH_PPI_PRIORITYR2_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 14, 2)
+#define ICH_PPI_PRIORITYR3_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 14, 3)
+#define ICH_PPI_PRIORITYR4_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 14, 4)
+#define ICH_PPI_PRIORITYR5_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 14, 5)
+#define ICH_PPI_PRIORITYR6_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 14, 6)
+#define ICH_PPI_PRIORITYR7_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 14, 7)
+#define ICH_PPI_PRIORITYR8_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 15, 0)
+#define ICH_PPI_PRIORITYR9_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 15, 1)
+#define ICH_PPI_PRIORITYR10_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 15, 2)
+#define ICH_PPI_PRIORITYR11_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 15, 3)
+#define ICH_PPI_PRIORITYR12_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 15, 4)
+#define ICH_PPI_PRIORITYR13_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 15, 5)
+#define ICH_PPI_PRIORITYR14_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 15, 6)
+#define ICH_PPI_PRIORITYR15_EL2 __MRS_REG_ALT_NAME(3, 4, 12, 15, 7)
+
+/*
+ * ICH_VCTLR_EL2
+ * Interrupt Controller Virtual CPU interface Control Register
+ */
+#define ICH_VCTLR_EL2 MRS_REG_ALT_NAME(ICH_VCTLR_EL2)
+#define ICH_VCTLR_EL2_op0 3
+#define ICH_VCTLR_EL2_op1 4
+#define ICH_VCTLR_EL2_CRn 12
+#define ICH_VCTLR_EL2_CRm 11
+#define ICH_VCTLR_EL2_op2 4
+#define ICH_VCTLR_V3 (0x1ul << 1)
+#define ICH_VCTLR_EN (0x1ul << 0)
+
+
/*
* IRS Config Frame registers
*/
#define IRS_IDR0 0x0000
+#define IRS_IDR0_VIRT (0x1u << 6)
#define IRS_IDR0_PA_RANGE_SHIFT 2
#define IRS_IDR0_PA_RANGE_MASK (0xfu << IRS_IDR0_PA_RANGE_SHIFT)
#define IRS_IDR0_PA_RANGE_4G (0x0u << IRS_IDR0_PA_RANGE_SHIFT)
@@ -528,25 +813,44 @@
#define IRS_IDR0_PA_RANGE_4P (0x6u << IRS_IDR0_PA_RANGE_SHIFT)
#define IRS_IDR0_PA_RANGE_64P (0x7u << IRS_IDR0_PA_RANGE_SHIFT)
#define IRS_IDR1 0x0004
+#define IRS_IDR0_PE_CNT_SHIFT 0
+#define IRS_IDR0_PE_CNT_MASK (0xffffu << IRS_IDR0_PE_CNT_SHIFT)
+#define IRS_IDR0_IAFFID_BITS_SHIFT 16
+#define IRS_IDR0_IAFFID_BITS_MASK (0x1fu << IRS_IDR0_IAFFID_BITS_SHIFT)
+#define IRS_IDR0_PRI_BITS_SHIFT 20
+#define IRS_IDR0_PRI_BITS_MASK (0x7u << IRS_IDR0_PRI_BITS_SHIFT)
#define IRS_IDR2 0x0008
#define IRS_IDR2_ISTMD_SZ_SHIFT 15
#define IRS_IDR2_ISTMD_SZ_MASK (0x1ful << IRS_IDR2_ISTMD_SZ_SHIFT)
-#define IRS_IRD2_ISTMD (0x1u << 14)
+#define IRS_IDR2_NO_ISTMD (0x0u << 14)
+#define IRS_IDR2_ISTMD (0x1u << 14)
#define IRS_IDR2_IST_L2SZ_64K (0x1u << 13)
#define IRS_IDR2_IST_L2SZ_16K (0x1u << 12)
#define IRS_IDR2_IST_L2SZ_4K (0x1u << 11)
-#define IRS_IDR2_IST_LEVELS (0x1u << 10)
+#define IRS_IDR2_IST_LEVELS_SINGLE (0x0u << 10)
+#define IRS_IDR2_IST_LEVELS_TWO (0x1u << 10)
#define IRS_IDR2_MIN_LPI_ID_BITS_SHIFT 6
#define IRS_IDR2_MIN_LPI_ID_BITS_MASK (0xful << IRS_IDR2_MIN_LPI_ID_BITS_SHIFT)
#define IRS_IDR2_MIN_LPI_ID_BITS(x) \
(((x) & IRS_IDR2_MIN_LPI_ID_BITS_MASK) >> IRS_IDR2_MIN_LPI_ID_BITS_SHIFT)
+#define IRS_IDR2_NO_PHYSICAL_LPI (0x0ul << 5)
#define IRS_IDR2_LPI (0x1ul << 5)
#define IRS_IDR2_ID_BITS_SHIFT 0
#define IRS_IDR2_ID_BITS_MASK (0x1ful << IRS_IDR2_ID_BITS_SHIFT)
#define IRS_IDR2_ID_BITS(x) \
(((x) & IRS_IDR2_ID_BITS_MASK) >> IRS_IDR2_ID_BITS_SHIFT)
#define IRS_IDR3 0x000c
+#define IRS_IDR3_VMT_LEVELS (1u << 10)
+#define IRS_IDR3_VM_ID_BITS_SHIFT 5
+#define IRS_IDR3_VM_ID_BITS_MASK (0x1fu << IRS_IDR3_VM_ID_BITS_SHIFT)
+#define IRS_IDR3_VMD_SZ_SHIFT 1
+#define IRS_IDR3_VMD_SZ_MASK (0xfu << IRS_IDR3_VM_ID_BITS_SHIFT)
+#define IRS_IDR3_VMD (0x1u << 0)
#define IRS_IDR4 0x0010
+#define IRS_IDR4_VPE_ID_BITS_SHIFT 6
+#define IRS_IDR4_VPE_ID_BITS_MASK (0xfu << IRS_IDR4_VPE_ID_BITS_SHIFT)
+#define IRS_IDR4_VPED_SZ_SHIFT 0
+#define IRS_IDR4_VPED_SZ_MASK (0x3fu << IRS_IDR4_VPED_SZ_SHIFT)
#define IRS_IDR5 0x0014
#define IRS_IDR5_SPI_RANGE 0x01ffffff
#define IRS_IDR6 0x0018
@@ -647,7 +951,13 @@
#define IRS_IST_STATUSR_IDLE (0x1u << 0)
#define IRS_MAP_L2_ISTR 0x01c0
#define IRS_VMT_BASER 0x0200
+#define IRS_VMT_BASER_ADDR_LIMIT 0x0100000000000000ul
+#define IRS_VMT_BASER_ADDR_MASK 0x00fffffffffffff8ul
+#define IRS_VMT_BASER_VALID (0x1ul << 0)
#define IRS_VMT_CFGR 0x0210
+#define IRS_VMT_CFGR_STRUCTURE (0x1u << 16)
+#define IRS_VMT_VM_ID_BITS_SHIFT 0
+#define IRS_VMT_VM_ID_BITS_MASK (0x1fu << IRS_VMT_VM_ID_BITS_SHIFT)
#define IRS_VMT_STATUSR 0x0214
#define IRS_VPE_SELR 0x0240
#define IRS_VPE_DBR 0x0248
@@ -657,10 +967,15 @@
#define IRS_VM_DBR 0x0280
#define IRS_VM_SELR 0x0288
#define IRS_VM_STATUSR 0x028c
+#define IRS_VMT_STATUSR_IDLE (0x1u << 0)
#define IRS_VMAP_L2_VMTR 0x02c0
#define IRS_VMAP_VMR 0x02c8
+#define IRS_VMAP_VMR_M (0x1ul << 63)
+#define IRS_VMAP_VMR_U (0x1ul << 62)
+#define IRS_VMAP_VMR_VM_ID_MASK 0xfffful
#define IRS_VMAP_VISTR 0x02d0
#define IRS_VMAP_L2_VISTR 0x02d8
+#define IRS_VMAP_L2_VISTR_M (0x1ul << 63)
#define IRS_VMAP_VPER 0x02e0
#define IRS_SAVE_VMR 0x0300
#define IRS_SAVE_VM_STATUSR 0x0308
@@ -682,6 +997,10 @@
#define L1_ISTE_VALID (0x1ul << 0)
/* L2_ISTE - Level 2 interrupt state table entry */
+#define ITSE_MAX_ADDR 0x00ffffffffffffff
+#define ITSE_ALIGN 8
+
+#define L2_ISTE_SIZE 4
#define L2_ISTE_IAFFID_SHIFT 16
#define L2_ISTE_IAFFID_MASK (0xffffu << L2_ISTE_IAFFID_SHIFT)
#define L2_ISTE_Priority_SHIFT 11
@@ -698,6 +1017,48 @@
#define L2_ISTE_LOG2_ENTRIES(istsz, l2sz) (10 - (istsz) + 2 * (l2sz))
#define L2_ISTE_LOG2_SIZE(l2sz) (11 + 2 * (l2sz) + 1)
+/* L2_VMTE - Level 2 VM table entry */
+#define L2_VMTE_SIZE 32
+
+#define L2_VMTE_SPI_ADDR_IDX 3
+#define L2_VMTE_SPI_ID_BITS_SHIFT 59
+#define L2_VMTE_SPI_ID_BITS_MASK (0x1fu << L2_VMTE_SPI_ID_BITS_SHIFT)
+#define L2_VMTE_SPI_IST_STRUCTURE (1u << 58)
+#define L2_VMTE_SPI_ISTSZ_SHIFT 56
+#define L2_VMTE_SPI_ISTSZ_MASK (0x3u << L2_VMTE_SPI_ISTSZ_SHIFT)
+#define L2_VMTE_SPI_IST_ADDR_MASK 0x00ffffffffffffc0ul
+#define L2_VMTE_SPI_IST_L2SZ_SHIFT 1
+#define L2_VMTE_SPI_IST_L2SZ_MASK (0x3u << L2_VMTE_SPI_IST_L2SZ_SHIFT)
+#define L2_VMTE_SPI_IST_VALID (0x1u << 0)
+
+#define L2_VMTE_LPI_ADDR_IDX 2
+#define L2_VMTE_LPI_ID_BITS_SHIFT 59
+#define L2_VMTE_LPI_ID_BITS_MASK (0x1fu << L2_VMTE_LPI_ID_BITS_SHIFT)
+#define L2_VMTE_LPI_IST_STRUCTURE (1u << 58)
+#define L2_VMTE_LPI_ISTSZ_SHIFT 56
+#define L2_VMTE_LPI_ISTSZ_MASK (0x3u << L2_VMTE_LPI_ISTSZ_SHIFT)
+#define L2_VMTE_LPI_IST_ADDR_MASK 0x00ffffffffffffc0ul
+#define L2_VMTE_LPI_IST_L2SZ_SHIFT 1
+#define L2_VMTE_LPI_IST_L2SZ_MASK (0x3u << L2_VMTE_LPI_IST_L2SZ_SHIFT)
+#define L2_VMTE_LPI_IST_VALID (0x1u << 0)
+
+#define L2_VMTE_VPE_ADDR_IDX 1
+#define L2_VMTE_VPE_ID_BITS_SHIFT 59
+#define L2_VMTE_VPE_ID_BITS_MASK (0x1fu << L2_VMTE_VPE_ID_BITS_SHIFT)
+#define L2_VMTE_VPET_ADDR_MASK 0x00fffffffffffff8ul
+
+#define L2_VMTE_VMD_ADDR_IDX 0
+#define L2_VMTE_VMD_ADDR_MASK 0x00fffffffffffff8ul
+#define L2_VMTE_VALID (0x1ul << 0)
+
+/* VPETE */
+#define VPETE_SIZE 8
+#define VPETE_VPED_ADDR_MASK 0x00ffffffffffffe0ul
+#define VPETE_VALID (0x1ul << 0)
+
+/* VPE_DESC - Virtual PE descriptor table entry */
+#define VPE_DESC_SIZE 32
+
/*
* Misc
*/